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https://github.com/c64scene-ar/llvm-6502.git
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b3f912b510
r186399 aggressively used the RISBG instruction for immediate ANDs, both because it can handle some values that AND IMMEDIATE can't, and because it allows the destination register to be different from the source. I realized later while implementing the distinct-ops support that it would be better to leave the choice up to convertToThreeAddress() instead. The AND IMMEDIATE form is shorter and is less likely to be cracked. This is a problem for 32-bit ANDs because we assume that all 32-bit operations will leave the high word untouched, whereas RISBG used in this way will either clear the high word or copy it from the source register. The patch uses the z196 instruction RISBLG for this instead. This means that z10 will be restricted to NILL, NILH and NILF for 32-bit ANDs, but I think that should be OK for now. Although we're using z10 as the base architecture, the optimization work is going to be focused more on z196 and zEC12. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187492 91177308-0d34-0410-b5e6-96231b3b80d8
172 lines
4.4 KiB
LLVM
172 lines
4.4 KiB
LLVM
; Test 64-bit atomic ANDs.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
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; Check ANDs of a variable.
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define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
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; CHECK-LABEL: f1:
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; CHECK: lg %r2, 0(%r3)
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; CHECK: [[LABEL:\.[^:]*]]:
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; CHECK: lgr %r0, %r2
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; CHECK: ngr %r0, %r4
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; CHECK: csg %r2, %r0, 0(%r3)
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; CHECK: jlh [[LABEL]]
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; CHECK: br %r14
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%res = atomicrmw and i64 *%src, i64 %b seq_cst
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ret i64 %res
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}
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; Check ANDs of 1, which are done using a register. (We could use RISBG
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; instead, but that isn't implemented yet.)
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define i64 @f2(i64 %dummy, i64 *%src) {
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; CHECK-LABEL: f2:
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; CHECK: ngr
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; CHECK: br %r14
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%res = atomicrmw and i64 *%src, i64 1 seq_cst
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ret i64 %res
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}
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; Check the equivalent of NIHF with 1, which can use RISBG instead.
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define i64 @f3(i64 %dummy, i64 *%src) {
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; CHECK-LABEL: f3:
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; CHECK: lg %r2, 0(%r3)
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; CHECK: [[LABEL:\.[^:]*]]:
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; CHECK: risbg %r0, %r2, 31, 191, 0
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; CHECK: csg %r2, %r0, 0(%r3)
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; CHECK: jlh [[LABEL]]
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; CHECK: br %r14
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%res = atomicrmw and i64 *%src, i64 8589934591 seq_cst
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ret i64 %res
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}
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; Check the lowest NIHF value outside the range of RISBG.
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define i64 @f4(i64 %dummy, i64 *%src) {
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; CHECK-LABEL: f4:
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; CHECK: lg %r2, 0(%r3)
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; CHECK: [[LABEL:\.[^:]*]]:
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; CHECK: lgr %r0, %r2
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; CHECK: nihf %r0, 2
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; CHECK: csg %r2, %r0, 0(%r3)
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; CHECK: jlh [[LABEL]]
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; CHECK: br %r14
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%res = atomicrmw and i64 *%src, i64 12884901887 seq_cst
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ret i64 %res
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}
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; Check the next value up, which must use a register.
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define i64 @f5(i64 %dummy, i64 *%src) {
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; CHECK-LABEL: f5:
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; CHECK: ngr
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; CHECK: br %r14
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%res = atomicrmw and i64 *%src, i64 12884901888 seq_cst
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ret i64 %res
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}
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; Check the lowest NIHH value outside the range of RISBG.
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define i64 @f6(i64 %dummy, i64 *%src) {
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; CHECK-LABEL: f6:
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; CHECK: nihh {{%r[0-5]}}, 2
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; CHECK: br %r14
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%res = atomicrmw and i64 *%src, i64 844424930131967 seq_cst
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ret i64 %res
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}
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; Check the next value up, which must use a register.
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define i64 @f7(i64 %dummy, i64 *%src) {
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; CHECK-LABEL: f7:
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; CHECK: ngr
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; CHECK: br %r14
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%res = atomicrmw and i64 *%src, i64 281474976710656 seq_cst
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ret i64 %res
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}
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; Check the highest NILL value outside the range of RISBG.
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define i64 @f8(i64 %dummy, i64 *%src) {
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; CHECK-LABEL: f8:
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; CHECK: nill {{%r[0-5]}}, 65530
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; CHECK: br %r14
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%res = atomicrmw and i64 *%src, i64 -6 seq_cst
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ret i64 %res
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}
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; Check the lowest NILL value outside the range of RISBG.
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define i64 @f9(i64 %dummy, i64 *%src) {
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; CHECK-LABEL: f9:
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; CHECK: nill {{%r[0-5]}}, 2
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; CHECK: br %r14
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%res = atomicrmw and i64 *%src, i64 -65534 seq_cst
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ret i64 %res
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}
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; Check the highest useful NILF value.
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define i64 @f10(i64 %dummy, i64 *%src) {
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; CHECK-LABEL: f10:
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; CHECK: nilf {{%r[0-5]}}, 4294901758
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; CHECK: br %r14
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%res = atomicrmw and i64 *%src, i64 -65538 seq_cst
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ret i64 %res
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}
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; Check the highest NILH value outside the range of RISBG.
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define i64 @f11(i64 %dummy, i64 *%src) {
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; CHECK-LABEL: f11:
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; CHECK: nilh {{%r[0-5]}}, 65530
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; CHECK: br %r14
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%res = atomicrmw and i64 *%src, i64 -327681 seq_cst
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ret i64 %res
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}
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; Check the lowest NILH value outside the range of RISBG.
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define i64 @f12(i64 %dummy, i64 *%src) {
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; CHECK-LABEL: f12:
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; CHECK: nilh {{%r[0-5]}}, 2
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; CHECK: br %r14
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%res = atomicrmw and i64 *%src, i64 -4294770689 seq_cst
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ret i64 %res
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}
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; Check the lowest NILF value outside the range of RISBG.
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define i64 @f13(i64 %dummy, i64 *%src) {
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; CHECK-LABEL: f13:
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; CHECK: nilf {{%r[0-5]}}, 2
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; CHECK: br %r14
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%res = atomicrmw and i64 *%src, i64 -4294967294 seq_cst
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ret i64 %res
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}
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; Check the highest NIHL value outside the range of RISBG.
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define i64 @f14(i64 %dummy, i64 *%src) {
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; CHECK-LABEL: f14:
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; CHECK: nihl {{%r[0-5]}}, 65530
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; CHECK: br %r14
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%res = atomicrmw and i64 *%src, i64 -21474836481 seq_cst
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ret i64 %res
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}
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; Check the lowest NIHL value outside the range of RISBG.
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define i64 @f15(i64 %dummy, i64 *%src) {
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; CHECK-LABEL: f15:
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; CHECK: nihl {{%r[0-5]}}, 2
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; CHECK: br %r14
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%res = atomicrmw and i64 *%src, i64 -281462091808769 seq_cst
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ret i64 %res
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}
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; Check the highest NIHH value outside the range of RISBG.
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define i64 @f16(i64 %dummy, i64 *%src) {
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; CHECK-LABEL: f16:
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; CHECK: nihh {{%r[0-5]}}, 65530
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; CHECK: br %r14
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%res = atomicrmw and i64 *%src, i64 -1407374883553281 seq_cst
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ret i64 %res
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}
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; Check the highest useful NIHF value.
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define i64 @f17(i64 %dummy, i64 *%src) {
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; CHECK-LABEL: f17:
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; CHECK: nihf {{%r[0-5]}}, 4294901758
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; CHECK: br %r14
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%res = atomicrmw and i64 *%src, i64 -281479271677953 seq_cst
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ret i64 %res
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}
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