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https://github.com/c64scene-ar/llvm-6502.git
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c498b0281f
MachineOperand auxInfo. Previous clunky implementation uses an external map to track sub-register uses. That works because register allocator uses a new virtual register for each spilled use. With interval splitting (coming soon), we may have multiple uses of the same register some of which are of using different sub-registers from others. It's too fragile to constantly update the information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44104 91177308-0d34-0410-b5e6-96231b3b80d8
446 lines
14 KiB
C++
446 lines
14 KiB
C++
//===-- MachineInstr.cpp --------------------------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Methods common to all machine instructions.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/MRegisterInfo.h"
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#include "llvm/Support/LeakDetector.h"
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#include "llvm/Support/Streams.h"
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#include <ostream>
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using namespace llvm;
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/// MachineInstr ctor - This constructor creates a dummy MachineInstr with
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/// TID NULL and no operands.
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MachineInstr::MachineInstr()
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: TID(0), NumImplicitOps(0), parent(0) {
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// Make sure that we get added to a machine basicblock
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LeakDetector::addGarbageObject(this);
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}
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void MachineInstr::addImplicitDefUseOperands() {
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if (TID->ImplicitDefs)
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for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs) {
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MachineOperand Op;
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Op.opType = MachineOperand::MO_Register;
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Op.IsDef = true;
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Op.IsImp = true;
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Op.IsKill = false;
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Op.IsDead = false;
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Op.contents.RegNo = *ImpDefs;
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Op.auxInfo.subReg = 0;
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Operands.push_back(Op);
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}
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if (TID->ImplicitUses)
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for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses) {
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MachineOperand Op;
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Op.opType = MachineOperand::MO_Register;
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Op.IsDef = false;
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Op.IsImp = true;
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Op.IsKill = false;
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Op.IsDead = false;
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Op.contents.RegNo = *ImpUses;
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Op.auxInfo.subReg = 0;
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Operands.push_back(Op);
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}
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}
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/// MachineInstr ctor - This constructor create a MachineInstr and add the
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/// implicit operands. It reserves space for number of operands specified by
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/// TargetInstrDescriptor or the numOperands if it is not zero. (for
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/// instructions with variable number of operands).
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MachineInstr::MachineInstr(const TargetInstrDescriptor &tid, bool NoImp)
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: TID(&tid), NumImplicitOps(0), parent(0) {
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if (!NoImp && TID->ImplicitDefs)
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for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
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NumImplicitOps++;
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if (!NoImp && TID->ImplicitUses)
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for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
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NumImplicitOps++;
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Operands.reserve(NumImplicitOps + TID->numOperands);
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if (!NoImp)
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addImplicitDefUseOperands();
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// Make sure that we get added to a machine basicblock
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LeakDetector::addGarbageObject(this);
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}
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/// MachineInstr ctor - Work exactly the same as the ctor above, except that the
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/// MachineInstr is created and added to the end of the specified basic block.
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///
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MachineInstr::MachineInstr(MachineBasicBlock *MBB,
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const TargetInstrDescriptor &tid)
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: TID(&tid), NumImplicitOps(0), parent(0) {
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assert(MBB && "Cannot use inserting ctor with null basic block!");
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if (TID->ImplicitDefs)
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for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
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NumImplicitOps++;
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if (TID->ImplicitUses)
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for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
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NumImplicitOps++;
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Operands.reserve(NumImplicitOps + TID->numOperands);
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addImplicitDefUseOperands();
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// Make sure that we get added to a machine basicblock
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LeakDetector::addGarbageObject(this);
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MBB->push_back(this); // Add instruction to end of basic block!
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}
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/// MachineInstr ctor - Copies MachineInstr arg exactly
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///
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MachineInstr::MachineInstr(const MachineInstr &MI) {
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TID = MI.getInstrDescriptor();
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NumImplicitOps = MI.NumImplicitOps;
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Operands.reserve(MI.getNumOperands());
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// Add operands
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for (unsigned i = 0; i != MI.getNumOperands(); ++i)
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Operands.push_back(MI.getOperand(i));
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// Set parent, next, and prev to null
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parent = 0;
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prev = 0;
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next = 0;
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}
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MachineInstr::~MachineInstr() {
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LeakDetector::removeGarbageObject(this);
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}
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/// getOpcode - Returns the opcode of this MachineInstr.
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///
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int MachineInstr::getOpcode() const {
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return TID->Opcode;
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}
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/// removeFromParent - This method unlinks 'this' from the containing basic
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/// block, and returns it, but does not delete it.
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MachineInstr *MachineInstr::removeFromParent() {
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assert(getParent() && "Not embedded in a basic block!");
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getParent()->remove(this);
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return this;
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}
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/// OperandComplete - Return true if it's illegal to add a new operand
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///
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bool MachineInstr::OperandsComplete() const {
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unsigned short NumOperands = TID->numOperands;
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if ((TID->Flags & M_VARIABLE_OPS) == 0 &&
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getNumOperands()-NumImplicitOps >= NumOperands)
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return true; // Broken: we have all the operands of this instruction!
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return false;
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}
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/// getNumExplicitOperands - Returns the number of non-implicit operands.
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///
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unsigned MachineInstr::getNumExplicitOperands() const {
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unsigned NumOperands = TID->numOperands;
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if ((TID->Flags & M_VARIABLE_OPS) == 0)
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return NumOperands;
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for (unsigned e = getNumOperands(); NumOperands != e; ++NumOperands) {
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const MachineOperand &MO = getOperand(NumOperands);
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if (!MO.isRegister() || !MO.isImplicit())
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NumOperands++;
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}
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return NumOperands;
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}
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/// isIdenticalTo - Return true if this operand is identical to the specified
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/// operand.
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bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
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if (getType() != Other.getType()) return false;
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switch (getType()) {
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default: assert(0 && "Unrecognized operand type");
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case MachineOperand::MO_Register:
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return getReg() == Other.getReg() && isDef() == Other.isDef();
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case MachineOperand::MO_Immediate:
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return getImm() == Other.getImm();
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case MachineOperand::MO_MachineBasicBlock:
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return getMBB() == Other.getMBB();
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case MachineOperand::MO_FrameIndex:
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return getFrameIndex() == Other.getFrameIndex();
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case MachineOperand::MO_ConstantPoolIndex:
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return getConstantPoolIndex() == Other.getConstantPoolIndex() &&
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getOffset() == Other.getOffset();
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case MachineOperand::MO_JumpTableIndex:
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return getJumpTableIndex() == Other.getJumpTableIndex();
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case MachineOperand::MO_GlobalAddress:
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return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
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case MachineOperand::MO_ExternalSymbol:
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return !strcmp(getSymbolName(), Other.getSymbolName()) &&
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getOffset() == Other.getOffset();
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}
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}
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/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
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/// the specific register or -1 if it is not found. It further tightening
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/// the search criteria to a use that kills the register if isKill is true.
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int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill) const {
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for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = getOperand(i);
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if (MO.isRegister() && MO.isUse() && MO.getReg() == Reg)
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if (!isKill || MO.isKill())
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return i;
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}
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return -1;
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}
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/// findRegisterDefOperand() - Returns the MachineOperand that is a def of
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/// the specific register or NULL if it is not found.
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MachineOperand *MachineInstr::findRegisterDefOperand(unsigned Reg) {
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for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
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MachineOperand &MO = getOperand(i);
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if (MO.isRegister() && MO.isDef() && MO.getReg() == Reg)
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return &MO;
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}
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return NULL;
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}
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/// findFirstPredOperandIdx() - Find the index of the first operand in the
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/// operand list that is used to represent the predicate. It returns -1 if
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/// none is found.
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int MachineInstr::findFirstPredOperandIdx() const {
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const TargetInstrDescriptor *TID = getInstrDescriptor();
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if (TID->Flags & M_PREDICABLE) {
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for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
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if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND))
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return i;
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}
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return -1;
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}
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/// isRegReDefinedByTwoAddr - Returns true if the Reg re-definition is due
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/// to two addr elimination.
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bool MachineInstr::isRegReDefinedByTwoAddr(unsigned Reg) const {
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const TargetInstrDescriptor *TID = getInstrDescriptor();
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for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
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const MachineOperand &MO1 = getOperand(i);
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if (MO1.isRegister() && MO1.isDef() && MO1.getReg() == Reg) {
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for (unsigned j = i+1; j < e; ++j) {
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const MachineOperand &MO2 = getOperand(j);
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if (MO2.isRegister() && MO2.isUse() && MO2.getReg() == Reg &&
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TID->getOperandConstraint(j, TOI::TIED_TO) == (int)i)
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return true;
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}
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}
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}
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return false;
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}
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/// copyKillDeadInfo - Copies kill / dead operand properties from MI.
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///
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void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (!MO.isRegister() || (!MO.isKill() && !MO.isDead()))
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continue;
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for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
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MachineOperand &MOp = getOperand(j);
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if (!MOp.isIdenticalTo(MO))
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continue;
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if (MO.isKill())
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MOp.setIsKill();
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else
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MOp.setIsDead();
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break;
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}
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}
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}
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/// copyPredicates - Copies predicate operand(s) from MI.
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void MachineInstr::copyPredicates(const MachineInstr *MI) {
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const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
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if (TID->Flags & M_PREDICABLE) {
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) {
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const MachineOperand &MO = MI->getOperand(i);
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// Predicated operands must be last operands.
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if (MO.isRegister())
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addRegOperand(MO.getReg(), false);
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else {
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addImmOperand(MO.getImm());
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}
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}
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}
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}
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}
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void MachineInstr::dump() const {
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cerr << " " << *this;
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}
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static inline void OutputReg(std::ostream &os, unsigned RegNo,
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const MRegisterInfo *MRI = 0) {
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if (!RegNo || MRegisterInfo::isPhysicalRegister(RegNo)) {
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if (MRI)
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os << "%" << MRI->get(RegNo).Name;
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else
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os << "%mreg(" << RegNo << ")";
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} else
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os << "%reg" << RegNo;
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}
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static void print(const MachineOperand &MO, std::ostream &OS,
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const TargetMachine *TM) {
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const MRegisterInfo *MRI = 0;
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if (TM) MRI = TM->getRegisterInfo();
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switch (MO.getType()) {
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case MachineOperand::MO_Register:
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OutputReg(OS, MO.getReg(), MRI);
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break;
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case MachineOperand::MO_Immediate:
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OS << MO.getImmedValue();
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break;
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case MachineOperand::MO_MachineBasicBlock:
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OS << "mbb<"
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<< ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
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<< "," << (void*)MO.getMachineBasicBlock() << ">";
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break;
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case MachineOperand::MO_FrameIndex:
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OS << "<fi#" << MO.getFrameIndex() << ">";
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break;
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case MachineOperand::MO_ConstantPoolIndex:
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OS << "<cp#" << MO.getConstantPoolIndex() << ">";
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break;
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case MachineOperand::MO_JumpTableIndex:
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OS << "<jt#" << MO.getJumpTableIndex() << ">";
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break;
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case MachineOperand::MO_GlobalAddress:
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OS << "<ga:" << ((Value*)MO.getGlobal())->getName();
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if (MO.getOffset()) OS << "+" << MO.getOffset();
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OS << ">";
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break;
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case MachineOperand::MO_ExternalSymbol:
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OS << "<es:" << MO.getSymbolName();
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if (MO.getOffset()) OS << "+" << MO.getOffset();
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OS << ">";
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break;
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default:
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assert(0 && "Unrecognized operand type");
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}
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}
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void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
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unsigned StartOp = 0;
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// Specialize printing if op#0 is definition
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if (getNumOperands() && getOperand(0).isRegister() && getOperand(0).isDef()) {
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::print(getOperand(0), OS, TM);
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if (getOperand(0).isDead())
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OS << "<dead>";
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OS << " = ";
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++StartOp; // Don't print this operand again!
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}
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if (TID)
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OS << TID->Name;
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for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
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const MachineOperand& mop = getOperand(i);
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if (i != StartOp)
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OS << ",";
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OS << " ";
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::print(mop, OS, TM);
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if (mop.isRegister()) {
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if (mop.isDef() || mop.isKill() || mop.isDead() || mop.isImplicit()) {
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OS << "<";
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bool NeedComma = false;
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if (mop.isImplicit()) {
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OS << (mop.isDef() ? "imp-def" : "imp-use");
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NeedComma = true;
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} else if (mop.isDef()) {
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OS << "def";
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NeedComma = true;
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}
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if (mop.isKill() || mop.isDead()) {
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if (NeedComma)
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OS << ",";
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if (mop.isKill())
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OS << "kill";
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if (mop.isDead())
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OS << "dead";
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}
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OS << ">";
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}
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}
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}
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OS << "\n";
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}
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void MachineInstr::print(std::ostream &os) const {
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// If the instruction is embedded into a basic block, we can find the target
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// info for the instruction.
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if (const MachineBasicBlock *MBB = getParent()) {
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const MachineFunction *MF = MBB->getParent();
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if (MF)
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print(os, &MF->getTarget());
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else
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print(os, 0);
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}
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// Otherwise, print it out in the "raw" format without symbolic register names
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// and such.
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os << getInstrDescriptor()->Name;
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for (unsigned i = 0, N = getNumOperands(); i < N; i++) {
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os << "\t" << getOperand(i);
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if (getOperand(i).isRegister() && getOperand(i).isDef())
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os << "<d>";
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}
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os << "\n";
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}
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void MachineOperand::print(std::ostream &OS) const {
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switch (getType()) {
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case MO_Register:
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OutputReg(OS, getReg());
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break;
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case MO_Immediate:
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OS << (long)getImmedValue();
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break;
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case MO_MachineBasicBlock:
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OS << "<mbb:"
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<< ((Value*)getMachineBasicBlock()->getBasicBlock())->getName()
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<< "@" << (void*)getMachineBasicBlock() << ">";
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break;
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case MO_FrameIndex:
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OS << "<fi#" << getFrameIndex() << ">";
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break;
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case MO_ConstantPoolIndex:
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OS << "<cp#" << getConstantPoolIndex() << ">";
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break;
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case MO_JumpTableIndex:
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OS << "<jt#" << getJumpTableIndex() << ">";
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break;
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case MO_GlobalAddress:
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OS << "<ga:" << ((Value*)getGlobal())->getName() << ">";
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break;
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case MO_ExternalSymbol:
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OS << "<es:" << getSymbolName() << ">";
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break;
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default:
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assert(0 && "Unrecognized operand type");
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break;
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}
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}
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