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	utils/sort_includes.py. I clearly haven't done this in a while, so more changed than usual. This even uncovered a missing include from the InstrProf library that I've added. No functionality changed here, just mechanical cleanup of the include order. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225974 91177308-0d34-0410-b5e6-96231b3b80d8
		
			
				
	
	
		
			71 lines
		
	
	
		
			2.3 KiB
		
	
	
	
		
			C++
		
	
	
	
	
	
			
		
		
	
	
			71 lines
		
	
	
		
			2.3 KiB
		
	
	
	
		
			C++
		
	
	
	
	
	
| //===-- MSP430TargetMachine.cpp - Define TargetMachine for MSP430 ---------===//
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| //
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| //                     The LLVM Compiler Infrastructure
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| //
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| // This file is distributed under the University of Illinois Open Source
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| // License. See LICENSE.TXT for details.
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| //
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| //===----------------------------------------------------------------------===//
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| //
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| // Top-level implementation for the MSP430 target.
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| //
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| //===----------------------------------------------------------------------===//
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| 
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| #include "MSP430TargetMachine.h"
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| #include "MSP430.h"
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| #include "llvm/CodeGen/Passes.h"
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| #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
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| #include "llvm/MC/MCAsmInfo.h"
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| #include "llvm/PassManager.h"
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| #include "llvm/Support/TargetRegistry.h"
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| using namespace llvm;
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| 
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| extern "C" void LLVMInitializeMSP430Target() {
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|   // Register the target.
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|   RegisterTargetMachine<MSP430TargetMachine> X(TheMSP430Target);
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| }
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| 
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| MSP430TargetMachine::MSP430TargetMachine(const Target &T, StringRef TT,
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|                                          StringRef CPU, StringRef FS,
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|                                          const TargetOptions &Options,
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|                                          Reloc::Model RM, CodeModel::Model CM,
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|                                          CodeGenOpt::Level OL)
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|     : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
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|       TLOF(make_unique<TargetLoweringObjectFileELF>()),
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|       Subtarget(TT, CPU, FS, *this) {
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|   initAsmInfo();
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| }
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| 
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| MSP430TargetMachine::~MSP430TargetMachine() {}
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| 
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| namespace {
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| /// MSP430 Code Generator Pass Configuration Options.
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| class MSP430PassConfig : public TargetPassConfig {
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| public:
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|   MSP430PassConfig(MSP430TargetMachine *TM, PassManagerBase &PM)
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|     : TargetPassConfig(TM, PM) {}
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| 
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|   MSP430TargetMachine &getMSP430TargetMachine() const {
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|     return getTM<MSP430TargetMachine>();
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|   }
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| 
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|   bool addInstSelector() override;
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|   void addPreEmitPass() override;
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| };
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| } // namespace
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| 
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| TargetPassConfig *MSP430TargetMachine::createPassConfig(PassManagerBase &PM) {
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|   return new MSP430PassConfig(this, PM);
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| }
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| 
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| bool MSP430PassConfig::addInstSelector() {
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|   // Install an instruction selector.
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|   addPass(createMSP430ISelDag(getMSP430TargetMachine(), getOptLevel()));
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|   return false;
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| }
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| 
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| void MSP430PassConfig::addPreEmitPass() {
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|   // Must run branch selection immediately preceding the asm printer.
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|   addPass(createMSP430BranchSelectionPass(), false);
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| }
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