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https://github.com/c64scene-ar/llvm-6502.git
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5e487f8dc7
This teaches the AArch64 backend to deal with the operations required to deal with the operations on v4f16 and v8f16 which are exposed by NEON intrinsics, plus the add, sub, mul and div operations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216555 91177308-0d34-0410-b5e6-96231b3b80d8
123 lines
2.8 KiB
LLVM
123 lines
2.8 KiB
LLVM
; RUN: llc < %s -mtriple=aarch64-none-eabi | FileCheck %s
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define <4 x half> @add_h(<4 x half> %a, <4 x half> %b) {
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entry:
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; CHECK-LABEL: add_h:
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; CHECK-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
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; CHECK-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
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; CHECK: fadd [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
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; CHECK: fcvtn v0.4h, [[RES]]
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%0 = fadd <4 x half> %a, %b
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ret <4 x half> %0
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}
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define <4 x half> @sub_h(<4 x half> %a, <4 x half> %b) {
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entry:
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; CHECK-LABEL: sub_h:
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; CHECK-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
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; CHECK-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
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; CHECK: fsub [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
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; CHECK: fcvtn v0.4h, [[RES]]
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%0 = fsub <4 x half> %a, %b
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ret <4 x half> %0
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}
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define <4 x half> @mul_h(<4 x half> %a, <4 x half> %b) {
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entry:
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; CHECK-LABEL: mul_h:
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; CHECK-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
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; CHECK-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
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; CHECK: fmul [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
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; CHECK: fcvtn v0.4h, [[RES]]
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%0 = fmul <4 x half> %a, %b
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ret <4 x half> %0
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}
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define <4 x half> @div_h(<4 x half> %a, <4 x half> %b) {
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entry:
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; CHECK-LABEL: div_h:
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; CHECK-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
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; CHECK-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
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; CHECK: fdiv [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
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; CHECK: fcvtn v0.4h, [[RES]]
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%0 = fdiv <4 x half> %a, %b
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ret <4 x half> %0
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}
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define <4 x half> @load_h(<4 x half>* %a) {
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entry:
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; CHECK-LABEL: load_h:
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; CHECK: ldr d0, [x0]
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%0 = load <4 x half>* %a, align 4
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ret <4 x half> %0
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}
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define void @store_h(<4 x half>* %a, <4 x half> %b) {
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entry:
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; CHECK-LABEL: store_h:
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; CHECK: str d0, [x0]
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store <4 x half> %b, <4 x half>* %a, align 4
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ret void
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}
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define <4 x half> @s_to_h(<4 x float> %a) {
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; CHECK-LABEL: s_to_h:
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; CHECK: fcvtn v0.4h, v0.4s
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%1 = fptrunc <4 x float> %a to <4 x half>
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ret <4 x half> %1
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}
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define <4 x half> @d_to_h(<4 x double> %a) {
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; CHECK-LABEL: d_to_h:
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; CHECK-DAG: fcvt
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; CHECK-DAG: fcvt
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; CHECK-DAG: fcvt
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; CHECK-DAG: fcvt
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; CHECK-DAG: ins
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; CHECK-DAG: ins
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; CHECK-DAG: ins
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; CHECK-DAG: ins
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%1 = fptrunc <4 x double> %a to <4 x half>
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ret <4 x half> %1
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}
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define <4 x float> @h_to_s(<4 x half> %a) {
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; CHECK-LABEL: h_to_s:
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; CHECK: fcvtl v0.4s, v0.4h
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%1 = fpext <4 x half> %a to <4 x float>
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ret <4 x float> %1
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}
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define <4 x double> @h_to_d(<4 x half> %a) {
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; CHECK-LABEL: h_to_d:
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; CHECK-DAG: fcvt
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; CHECK-DAG: fcvt
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; CHECK-DAG: fcvt
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; CHECK-DAG: fcvt
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; CHECK-DAG: ins
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; CHECK-DAG: ins
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; CHECK-DAG: ins
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; CHECK-DAG: ins
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%1 = fpext <4 x half> %a to <4 x double>
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ret <4 x double> %1
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}
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define <4 x half> @bitcast_i_to_h(float, <4 x i16> %a) {
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; CHECK-LABEL: bitcast_i_to_h:
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; CHECK: mov v0.16b, v1.16b
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%2 = bitcast <4 x i16> %a to <4 x half>
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ret <4 x half> %2
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}
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define <4 x i16> @bitcast_h_to_i(float, <4 x half> %a) {
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; CHECK-LABEL: bitcast_h_to_i:
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; CHECK: mov v0.16b, v1.16b
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%2 = bitcast <4 x half> %a to <4 x i16>
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ret <4 x i16> %2
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}
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