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1f996fa36b
This is equivalent to the AMDGPUTargetMachine now, but it is the starting point for separating R600 and GCN functionality into separate targets. It is recommened that users start using the gcn triple for GCN-based GPUs, because using the r600 triple for these GPUs will be deprecated in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225277 91177308-0d34-0410-b5e6-96231b3b80d8
35 lines
1.1 KiB
LLVM
35 lines
1.1 KiB
LLVM
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK
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; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK
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; R600-CHECK: {{^}}build_vector2:
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; R600-CHECK: MOV
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; R600-CHECK: MOV
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; R600-CHECK-NOT: MOV
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; SI-CHECK: {{^}}build_vector2:
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; SI-CHECK-DAG: v_mov_b32_e32 v[[X:[0-9]]], 5
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; SI-CHECK-DAG: v_mov_b32_e32 v[[Y:[0-9]]], 6
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; SI-CHECK: buffer_store_dwordx2 v{{\[}}[[X]]:[[Y]]{{\]}}
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define void @build_vector2 (<2 x i32> addrspace(1)* %out) {
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entry:
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store <2 x i32> <i32 5, i32 6>, <2 x i32> addrspace(1)* %out
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ret void
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}
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; R600-CHECK: {{^}}build_vector4:
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; R600-CHECK: MOV
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; R600-CHECK: MOV
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; R600-CHECK: MOV
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; R600-CHECK: MOV
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; R600-CHECK-NOT: MOV
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; SI-CHECK: {{^}}build_vector4:
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; SI-CHECK-DAG: v_mov_b32_e32 v[[X:[0-9]]], 5
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; SI-CHECK-DAG: v_mov_b32_e32 v[[Y:[0-9]]], 6
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; SI-CHECK-DAG: v_mov_b32_e32 v[[Z:[0-9]]], 7
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; SI-CHECK-DAG: v_mov_b32_e32 v[[W:[0-9]]], 8
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; SI-CHECK: buffer_store_dwordx4 v{{\[}}[[X]]:[[W]]{{\]}}
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define void @build_vector4 (<4 x i32> addrspace(1)* %out) {
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entry:
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store <4 x i32> <i32 5, i32 6, i32 7, i32 8>, <4 x i32> addrspace(1)* %out
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ret void
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}
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