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https://github.com/c64scene-ar/llvm-6502.git
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1f996fa36b
This is equivalent to the AMDGPUTargetMachine now, but it is the starting point for separating R600 and GCN functionality into separate targets. It is recommened that users start using the gcn triple for GCN-based GPUs, because using the r600 triple for these GPUs will be deprecated in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225277 91177308-0d34-0410-b5e6-96231b3b80d8
49 lines
1.8 KiB
LLVM
49 lines
1.8 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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declare i32 @llvm.r600.read.tidig.x() readnone
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; This is broken because the low half of the 64-bit add remains on the
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; SALU, but the upper half does not. The addc expects the carry bit
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; set in vcc, which is undefined since the low scalar half add sets
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; scc instead.
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; FUNC-LABEL: {{^}}imp_def_vcc_split_i64_add_0:
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; SI: v_add_i32
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; SI: v_addc_u32
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define void @imp_def_vcc_split_i64_add_0(i64 addrspace(1)* %out, i32 %val) {
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%vec.0 = insertelement <2 x i32> undef, i32 %val, i32 0
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%vec.1 = insertelement <2 x i32> %vec.0, i32 999999, i32 1
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%bc = bitcast <2 x i32> %vec.1 to i64
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%add = add i64 %bc, 399
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store i64 %add, i64 addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}imp_def_vcc_split_i64_add_1:
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; SI: v_add_i32
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; SI: v_addc_u32
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define void @imp_def_vcc_split_i64_add_1(i64 addrspace(1)* %out, i32 %val0, i64 %val1) {
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%vec.0 = insertelement <2 x i32> undef, i32 %val0, i32 0
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%vec.1 = insertelement <2 x i32> %vec.0, i32 99999, i32 1
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%bc = bitcast <2 x i32> %vec.1 to i64
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%add = add i64 %bc, %val1
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store i64 %add, i64 addrspace(1)* %out, align 8
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ret void
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}
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; Doesn't use constants
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; FUNC-LABEL @imp_def_vcc_split_i64_add_2
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; SI: v_add_i32
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; SI: v_addc_u32
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define void @imp_def_vcc_split_i64_add_2(i64 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %val0, i64 %val1) {
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%tid = call i32 @llvm.r600.read.tidig.x() readnone
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%gep = getelementptr i32 addrspace(1)* %in, i32 %tid
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%load = load i32 addrspace(1)* %gep
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%vec.0 = insertelement <2 x i32> undef, i32 %val0, i32 0
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%vec.1 = insertelement <2 x i32> %vec.0, i32 %load, i32 1
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%bc = bitcast <2 x i32> %vec.1 to i64
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%add = add i64 %bc, %val1
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store i64 %add, i64 addrspace(1)* %out, align 8
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ret void
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}
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