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https://github.com/c64scene-ar/llvm-6502.git
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ff18b9ff38
The Cortex-M7 has 3 options for its FPU: none, FPv5-SP-D16 and FPv5-DP-D16. FPv5 has the same instructions as FP-ARMv8, so it can be modelled using the same target feature, and all double-precision operations are already disabled by the fp-only-sp target features. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218747 91177308-0d34-0410-b5e6-96231b3b80d8
28 lines
969 B
LLVM
28 lines
969 B
LLVM
; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -march=thumb -mcpu=cortex-m3 | FileCheck %s -check-prefix=CHECK -check-prefix=CORTEXM3
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; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -march=thumb -mcpu=cortex-m4 | FileCheck %s -check-prefix=CHECK -check-prefix=CORTEXM4
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; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -march=thumb -mcpu=cortex-m7 | FileCheck %s -check-prefix=CHECK -check-prefix=CORTEXM7
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; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -march=thumb -mcpu=cortex-a8 | FileCheck %s -check-prefix=CHECK -check-prefix=CORTEXA8
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define float @foo(float %a, float %b) {
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entry:
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; CHECK-LABEL: foo:
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; CORTEXM3: bl ___mulsf3
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; CORTEXM4: vmul.f32 s
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; CORTEXM7: vmul.f32 s
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; CORTEXA8: vmul.f32 d
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%0 = fmul float %a, %b
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ret float %0
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}
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define double @bar(double %a, double %b) {
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entry:
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; CHECK-LABEL: bar:
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%0 = fmul double %a, %b
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; CORTEXM3: bl ___muldf3
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; CORTEXM4: {{bl|b.w}} ___muldf3
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; CORTEXM7: vmul.f64 d
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; CORTEXA8: vmul.f64 d
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ret double %0
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}
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