mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-10-31 08:16:47 +00:00
ff18b9ff38
The Cortex-M7 has 3 options for its FPU: none, FPv5-SP-D16 and FPv5-DP-D16. FPv5 has the same instructions as FP-ARMv8, so it can be modelled using the same target feature, and all double-precision operations are already disabled by the fp-only-sp target features. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218747 91177308-0d34-0410-b5e6-96231b3b80d8
302 lines
6.8 KiB
LLVM
302 lines
6.8 KiB
LLVM
; RUN: llc < %s -mtriple=thumbv7-none-eabi -mcpu=cortex-m3 | FileCheck %s -check-prefix=CHECK -check-prefix=NONE
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; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m4 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=SP
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; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m7 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP
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; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-a8 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP
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define i1 @cmp_f_false(float %a, float %b) {
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; CHECK-LABEL: cmp_f_false:
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; NONE: movs r0, #0
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; HARD: movs r0, #0
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%1 = fcmp false float %a, %b
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ret i1 %1
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}
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define i1 @cmp_f_oeq(float %a, float %b) {
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; CHECK-LABEL: cmp_f_oeq:
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; NONE: bl __aeabi_fcmpeq
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; HARD: vcmpe.f32
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; HARD: moveq r0, #1
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%1 = fcmp oeq float %a, %b
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ret i1 %1
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}
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define i1 @cmp_f_ogt(float %a, float %b) {
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; CHECK-LABEL: cmp_f_ogt:
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; NONE: bl __aeabi_fcmpgt
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; HARD: vcmpe.f32
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; HARD: movgt r0, #1
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%1 = fcmp ogt float %a, %b
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ret i1 %1
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}
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define i1 @cmp_f_oge(float %a, float %b) {
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; CHECK-LABEL: cmp_f_oge:
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; NONE: bl __aeabi_fcmpge
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; HARD: vcmpe.f32
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; HARD: movge r0, #1
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%1 = fcmp oge float %a, %b
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ret i1 %1
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}
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define i1 @cmp_f_olt(float %a, float %b) {
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; CHECK-LABEL: cmp_f_olt:
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; NONE: bl __aeabi_fcmplt
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; HARD: vcmpe.f32
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; HARD: movmi r0, #1
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%1 = fcmp olt float %a, %b
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ret i1 %1
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}
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define i1 @cmp_f_ole(float %a, float %b) {
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; CHECK-LABEL: cmp_f_ole:
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; NONE: bl __aeabi_fcmple
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; HARD: vcmpe.f32
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; HARD: movls r0, #1
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%1 = fcmp ole float %a, %b
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ret i1 %1
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}
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define i1 @cmp_f_one(float %a, float %b) {
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; CHECK-LABEL: cmp_f_one:
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; NONE: bl __aeabi_fcmpgt
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; NONE: bl __aeabi_fcmplt
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; HARD: vcmpe.f32
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; HARD: movmi r0, #1
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; HARD: movgt r0, #1
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%1 = fcmp one float %a, %b
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ret i1 %1
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}
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define i1 @cmp_f_ord(float %a, float %b) {
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; CHECK-LABEL: cmp_f_ord:
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; NONE: bl __aeabi_fcmpun
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; HARD: vcmpe.f32
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; HARD: movvc r0, #1
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%1 = fcmp ord float %a, %b
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ret i1 %1
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}define i1 @cmp_f_ueq(float %a, float %b) {
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; CHECK-LABEL: cmp_f_ueq:
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; NONE: bl __aeabi_fcmpeq
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; NONE: bl __aeabi_fcmpun
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; HARD: vcmpe.f32
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; HARD: moveq r0, #1
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; HARD: movvs r0, #1
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%1 = fcmp ueq float %a, %b
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ret i1 %1
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}
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define i1 @cmp_f_ugt(float %a, float %b) {
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; CHECK-LABEL: cmp_f_ugt:
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; NONE: bl __aeabi_fcmpgt
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; NONE: bl __aeabi_fcmpun
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; HARD: vcmpe.f32
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; HARD: movhi r0, #1
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%1 = fcmp ugt float %a, %b
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ret i1 %1
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}
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define i1 @cmp_f_uge(float %a, float %b) {
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; CHECK-LABEL: cmp_f_uge:
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; NONE: bl __aeabi_fcmpge
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; NONE: bl __aeabi_fcmpun
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; HARD: vcmpe.f32
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; HARD: movpl r0, #1
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%1 = fcmp uge float %a, %b
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ret i1 %1
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}
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define i1 @cmp_f_ult(float %a, float %b) {
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; CHECK-LABEL: cmp_f_ult:
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; NONE: bl __aeabi_fcmplt
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; NONE: bl __aeabi_fcmpun
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; HARD: vcmpe.f32
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; HARD: movlt r0, #1
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%1 = fcmp ult float %a, %b
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ret i1 %1
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}
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define i1 @cmp_f_ule(float %a, float %b) {
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; CHECK-LABEL: cmp_f_ule:
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; NONE: bl __aeabi_fcmple
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; NONE: bl __aeabi_fcmpun
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; HARD: vcmpe.f32
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; HARD: movle r0, #1
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%1 = fcmp ule float %a, %b
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ret i1 %1
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}
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define i1 @cmp_f_une(float %a, float %b) {
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; CHECK-LABEL: cmp_f_une:
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; NONE: bl __aeabi_fcmpeq
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; HARD: vcmpe.f32
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; HARD: movne r0, #1
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%1 = fcmp une float %a, %b
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ret i1 %1
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}
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define i1 @cmp_f_uno(float %a, float %b) {
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; CHECK-LABEL: cmp_f_uno:
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; NONE: bl __aeabi_fcmpun
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; HARD: vcmpe.f32
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; HARD: movvs r0, #1
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%1 = fcmp uno float %a, %b
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ret i1 %1
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}
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define i1 @cmp_f_true(float %a, float %b) {
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; CHECK-LABEL: cmp_f_true:
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; NONE: movs r0, #1
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; HARD: movs r0, #1
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%1 = fcmp true float %a, %b
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ret i1 %1
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}
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define i1 @cmp_d_false(double %a, double %b) {
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; CHECK-LABEL: cmp_d_false:
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; NONE: movs r0, #0
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; HARD: movs r0, #0
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%1 = fcmp false double %a, %b
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ret i1 %1
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}
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define i1 @cmp_d_oeq(double %a, double %b) {
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; CHECK-LABEL: cmp_d_oeq:
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; NONE: bl __aeabi_dcmpeq
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; SP: bl __aeabi_dcmpeq
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; DP: vcmpe.f64
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; DP: moveq r0, #1
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%1 = fcmp oeq double %a, %b
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ret i1 %1
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}
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define i1 @cmp_d_ogt(double %a, double %b) {
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; CHECK-LABEL: cmp_d_ogt:
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; NONE: bl __aeabi_dcmpgt
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; SP: bl __aeabi_dcmpgt
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; DP: vcmpe.f64
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; DP: movgt r0, #1
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%1 = fcmp ogt double %a, %b
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ret i1 %1
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}
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define i1 @cmp_d_oge(double %a, double %b) {
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; CHECK-LABEL: cmp_d_oge:
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; NONE: bl __aeabi_dcmpge
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; SP: bl __aeabi_dcmpge
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; DP: vcmpe.f64
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; DP: movge r0, #1
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%1 = fcmp oge double %a, %b
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ret i1 %1
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}
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define i1 @cmp_d_olt(double %a, double %b) {
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; CHECK-LABEL: cmp_d_olt:
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; NONE: bl __aeabi_dcmplt
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; SP: bl __aeabi_dcmplt
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; DP: vcmpe.f64
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; DP: movmi r0, #1
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%1 = fcmp olt double %a, %b
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ret i1 %1
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}
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define i1 @cmp_d_ole(double %a, double %b) {
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; CHECK-LABEL: cmp_d_ole:
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; NONE: bl __aeabi_dcmple
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; SP: bl __aeabi_dcmple
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; DP: vcmpe.f64
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; DP: movls r0, #1
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%1 = fcmp ole double %a, %b
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ret i1 %1
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}
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define i1 @cmp_d_one(double %a, double %b) {
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; CHECK-LABEL: cmp_d_one:
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; NONE: bl __aeabi_dcmpgt
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; NONE: bl __aeabi_dcmplt
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; SP: bl __aeabi_dcmpgt
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; SP: bl __aeabi_dcmplt
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; DP: vcmpe.f64
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; DP: movmi r0, #1
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; DP: movgt r0, #1
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%1 = fcmp one double %a, %b
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ret i1 %1
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}
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define i1 @cmp_d_ord(double %a, double %b) {
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; CHECK-LABEL: cmp_d_ord:
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; NONE: bl __aeabi_dcmpun
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; SP: bl __aeabi_dcmpun
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; DP: vcmpe.f64
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; DP: movvc r0, #1
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%1 = fcmp ord double %a, %b
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ret i1 %1
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}
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define i1 @cmp_d_ugt(double %a, double %b) {
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; CHECK-LABEL: cmp_d_ugt:
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; NONE: bl __aeabi_dcmpgt
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; NONE: bl __aeabi_dcmpun
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; SP: bl __aeabi_dcmpgt
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; SP: bl __aeabi_dcmpun
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; DP: vcmpe.f64
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; DP: movhi r0, #1
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%1 = fcmp ugt double %a, %b
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ret i1 %1
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}
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define i1 @cmp_d_ult(double %a, double %b) {
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; CHECK-LABEL: cmp_d_ult:
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; NONE: bl __aeabi_dcmplt
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; NONE: bl __aeabi_dcmpun
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; SP: bl __aeabi_dcmplt
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; SP: bl __aeabi_dcmpun
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; DP: vcmpe.f64
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; DP: movlt r0, #1
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%1 = fcmp ult double %a, %b
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ret i1 %1
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}
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define i1 @cmp_d_uno(double %a, double %b) {
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; CHECK-LABEL: cmp_d_uno:
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; NONE: bl __aeabi_dcmpun
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; SP: bl __aeabi_dcmpun
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; DP: vcmpe.f64
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; DP: movvs r0, #1
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%1 = fcmp uno double %a, %b
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ret i1 %1
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}
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define i1 @cmp_d_true(double %a, double %b) {
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; CHECK-LABEL: cmp_d_true:
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; NONE: movs r0, #1
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; HARD: movs r0, #1
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%1 = fcmp true double %a, %b
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ret i1 %1
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}
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define i1 @cmp_d_ueq(double %a, double %b) {
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; CHECK-LABEL: cmp_d_ueq:
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; NONE: bl __aeabi_dcmpeq
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; NONE: bl __aeabi_dcmpun
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; SP: bl __aeabi_dcmpeq
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; SP: bl __aeabi_dcmpun
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; DP: vcmpe.f64
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; DP: moveq r0, #1
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; DP: movvs r0, #1
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%1 = fcmp ueq double %a, %b
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ret i1 %1
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}
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define i1 @cmp_d_uge(double %a, double %b) {
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; CHECK-LABEL: cmp_d_uge:
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; NONE: bl __aeabi_dcmpge
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; NONE: bl __aeabi_dcmpun
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; SP: bl __aeabi_dcmpge
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; SP: bl __aeabi_dcmpun
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; DP: vcmpe.f64
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; DP: movpl r0, #1
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%1 = fcmp uge double %a, %b
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ret i1 %1
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}
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define i1 @cmp_d_ule(double %a, double %b) {
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; CHECK-LABEL: cmp_d_ule:
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; NONE: bl __aeabi_dcmple
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; NONE: bl __aeabi_dcmpun
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; SP: bl __aeabi_dcmple
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; SP: bl __aeabi_dcmpun
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; DP: vcmpe.f64
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; DP: movle r0, #1
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%1 = fcmp ule double %a, %b
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ret i1 %1
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}
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define i1 @cmp_d_une(double %a, double %b) {
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; CHECK-LABEL: cmp_d_une:
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; NONE: bl __aeabi_dcmpeq
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; SP: bl __aeabi_dcmpeq
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; DP: vcmpe.f64
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; DP: movne r0, #1
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%1 = fcmp une double %a, %b
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ret i1 %1
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}
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