mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-10-31 08:16:47 +00:00
9d7038c437
Currently, we only codegen the VRINT[APMXZR] and VCVT[BT] instructions when targeting ARMv8, but they are actually present on any target with FP-ARMv8. Note that FP-ARMv8 is called FPv5 when is is part of an M-profile core, but they have the same instructions so we model them both as FPARMv8 in the ARM backend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218763 91177308-0d34-0410-b5e6-96231b3b80d8
222 lines
6.3 KiB
LLVM
222 lines
6.3 KiB
LLVM
; RUN: llc < %s -mtriple=thumbv7-none-eabi -mcpu=cortex-m3 | FileCheck %s -check-prefix=CHECK -check-prefix=SOFT -check-prefix=NONE
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; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m4 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=SP -check-prefix=VMLA
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; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m7 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=VFP -check-prefix=FP-ARMv8 -check-prefix=VMLA
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; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m7 -mattr=+fp-only-sp | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=SP -check-prefix=FP-ARMv8 -check-prefix=VMLA
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; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-a7 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=NEON -check-prefix=VFP4 -check-prefix=NO-VMLA
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; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-a57 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=NEON -check-prefix=FP-ARMv8 -check-prefix=VMLA
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declare float @llvm.sqrt.f32(float %Val)
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define float @sqrt_f(float %a) {
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; CHECK-LABEL: sqrt_f:
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; SOFT: bl sqrtf
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; HARD: vsqrt.f32 s0, s0
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%1 = call float @llvm.sqrt.f32(float %a)
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ret float %1
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}
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declare float @llvm.powi.f32(float %Val, i32 %power)
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define float @powi_f(float %a, i32 %b) {
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; CHECK-LABEL: powi_f:
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; SOFT: bl __powisf2
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; HARD: b __powisf2
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%1 = call float @llvm.powi.f32(float %a, i32 %b)
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ret float %1
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}
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declare float @llvm.sin.f32(float %Val)
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define float @sin_f(float %a) {
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; CHECK-LABEL: sin_f:
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; SOFT: bl sinf
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; HARD: b sinf
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%1 = call float @llvm.sin.f32(float %a)
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ret float %1
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}
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declare float @llvm.cos.f32(float %Val)
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define float @cos_f(float %a) {
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; CHECK-LABEL: cos_f:
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; SOFT: bl cosf
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; HARD: b cosf
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%1 = call float @llvm.cos.f32(float %a)
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ret float %1
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}
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declare float @llvm.pow.f32(float %Val, float %power)
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define float @pow_f(float %a, float %b) {
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; CHECK-LABEL: pow_f:
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; SOFT: bl powf
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; HARD: b powf
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%1 = call float @llvm.pow.f32(float %a, float %b)
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ret float %1
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}
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declare float @llvm.exp.f32(float %Val)
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define float @exp_f(float %a) {
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; CHECK-LABEL: exp_f:
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; SOFT: bl expf
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; HARD: b expf
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%1 = call float @llvm.exp.f32(float %a)
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ret float %1
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}
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declare float @llvm.exp2.f32(float %Val)
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define float @exp2_f(float %a) {
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; CHECK-LABEL: exp2_f:
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; SOFT: bl exp2f
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; HARD: b exp2f
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%1 = call float @llvm.exp2.f32(float %a)
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ret float %1
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}
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declare float @llvm.log.f32(float %Val)
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define float @log_f(float %a) {
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; CHECK-LABEL: log_f:
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; SOFT: bl logf
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; HARD: b logf
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%1 = call float @llvm.log.f32(float %a)
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ret float %1
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}
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declare float @llvm.log10.f32(float %Val)
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define float @log10_f(float %a) {
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; CHECK-LABEL: log10_f:
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; SOFT: bl log10f
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; HARD: b log10f
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%1 = call float @llvm.log10.f32(float %a)
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ret float %1
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}
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declare float @llvm.log2.f32(float %Val)
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define float @log2_f(float %a) {
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; CHECK-LABEL: log2_f:
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; SOFT: bl log2f
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; HARD: b log2f
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%1 = call float @llvm.log2.f32(float %a)
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ret float %1
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}
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declare float @llvm.fma.f32(float %a, float %b, float %c)
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define float @fma_f(float %a, float %b, float %c) {
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; CHECK-LABEL: fma_f:
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; SOFT: bl fmaf
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; HARD: vfma.f32
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%1 = call float @llvm.fma.f32(float %a, float %b, float %c)
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ret float %1
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}
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declare float @llvm.fabs.f32(float %Val)
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define float @abs_f(float %a) {
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; CHECK-LABEL: abs_f:
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; SOFT: bic r0, r0, #-2147483648
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; HARD: vabs.f32
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%1 = call float @llvm.fabs.f32(float %a)
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ret float %1
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}
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declare float @llvm.copysign.f32(float %Mag, float %Sgn)
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define float @copysign_f(float %a, float %b) {
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; CHECK-LABEL: copysign_f:
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; NONE: lsrs [[REG:r[0-9]+]], r{{[0-9]+}}, #31
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; NONE: bfi r{{[0-9]+}}, [[REG]], #31, #1
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; SP: lsrs [[REG:r[0-9]+]], r{{[0-9]+}}, #31
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; SP: bfi r{{[0-9]+}}, [[REG]], #31, #1
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; VFP: lsrs [[REG:r[0-9]+]], r{{[0-9]+}}, #31
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; VFP: bfi r{{[0-9]+}}, [[REG]], #31, #1
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; NEON: vmov.i32 [[REG:d[0-9]+]], #0x80000000
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; NEON: vbsl [[REG]], d
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%1 = call float @llvm.copysign.f32(float %a, float %b)
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ret float %1
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}
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declare float @llvm.floor.f32(float %Val)
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define float @floor_f(float %a) {
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; CHECK-LABEL: floor_f:
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; SOFT: bl floorf
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; VFP4: b floorf
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; FP-ARMv8: vrintm.f32
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%1 = call float @llvm.floor.f32(float %a)
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ret float %1
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}
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declare float @llvm.ceil.f32(float %Val)
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define float @ceil_f(float %a) {
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; CHECK-LABEL: ceil_f:
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; SOFT: bl ceilf
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; VFP4: b ceilf
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; FP-ARMv8: vrintp.f32
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%1 = call float @llvm.ceil.f32(float %a)
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ret float %1
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}
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declare float @llvm.trunc.f32(float %Val)
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define float @trunc_f(float %a) {
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; CHECK-LABEL: trunc_f:
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; SOFT: bl truncf
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; VFP4: b truncf
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; FP-ARMv8: vrintz.f32
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%1 = call float @llvm.trunc.f32(float %a)
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ret float %1
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}
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declare float @llvm.rint.f32(float %Val)
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define float @rint_f(float %a) {
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; CHECK-LABEL: rint_f:
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; SOFT: bl rintf
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; VFP4: b rintf
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; FP-ARMv8: vrintx.f32
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%1 = call float @llvm.rint.f32(float %a)
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ret float %1
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}
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declare float @llvm.nearbyint.f32(float %Val)
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define float @nearbyint_f(float %a) {
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; CHECK-LABEL: nearbyint_f:
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; SOFT: bl nearbyintf
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; VFP4: b nearbyintf
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; FP-ARMv8: vrintr.f32
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%1 = call float @llvm.nearbyint.f32(float %a)
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ret float %1
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}
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declare float @llvm.round.f32(float %Val)
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define float @round_f(float %a) {
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; CHECK-LABEL: round_f:
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; SOFT: bl roundf
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; VFP4: b roundf
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; FP-ARMv8: vrinta.f32
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%1 = call float @llvm.round.f32(float %a)
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ret float %1
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}
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; FIXME: why does cortex-m4 use vmla, while cortex-a7 uses vmul+vadd?
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; (these should be equivalent, even the rounding is the same)
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declare float @llvm.fmuladd.f32(float %a, float %b, float %c)
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define float @fmuladd_f(float %a, float %b, float %c) {
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; CHECK-LABEL: fmuladd_f:
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; SOFT: bl __aeabi_fmul
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; SOFT: bl __aeabi_fadd
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; VMLA: vmla.f32
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; NO-VMLA: vmul.f32
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; NO-VMLA: vadd.f32
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%1 = call float @llvm.fmuladd.f32(float %a, float %b, float %c)
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ret float %1
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}
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declare i16 @llvm.convert.to.fp16.f32(float %a)
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define i16 @f_to_h(float %a) {
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; CHECK-LABEL: f_to_h:
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; SOFT: bl __gnu_f2h_ieee
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; HARD: vcvt{{[bt]}}.f16.f32
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%1 = call i16 @llvm.convert.to.fp16.f32(float %a)
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ret i16 %1
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}
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declare float @llvm.convert.from.fp16.f32(i16 %a)
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define float @h_to_f(i16 %a) {
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; CHECK-LABEL: h_to_f:
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; SOFT: bl __gnu_h2f_ieee
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; HARD: vcvt{{[bt]}}.f32.f16
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%1 = call float @llvm.convert.from.fp16.f32(i16 %a)
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ret float %1
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}
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