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https://github.com/c64scene-ar/llvm-6502.git
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600f171486
The only folding these load/store architectures can do is converting COPY into a load or store, and the target independent part of foldMemoryOperand already knows how to do that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108099 91177308-0d34-0410-b5e6-96231b3b80d8
198 lines
7.7 KiB
C++
198 lines
7.7 KiB
C++
//===- SparcInstrInfo.cpp - Sparc Instruction Information -------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Sparc implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "SparcInstrInfo.h"
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#include "SparcSubtarget.h"
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#include "Sparc.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "SparcGenInstrInfo.inc"
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#include "SparcMachineFunctionInfo.h"
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using namespace llvm;
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SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST)
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: TargetInstrInfoImpl(SparcInsts, array_lengthof(SparcInsts)),
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RI(ST, *this), Subtarget(ST) {
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}
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static bool isZeroImm(const MachineOperand &op) {
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return op.isImm() && op.getImm() == 0;
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}
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/// Return true if the instruction is a register to register move and
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/// leave the source and dest operands in the passed parameters.
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///
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bool SparcInstrInfo::isMoveInstr(const MachineInstr &MI,
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unsigned &SrcReg, unsigned &DstReg,
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unsigned &SrcSR, unsigned &DstSR) const {
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SrcSR = DstSR = 0; // No sub-registers.
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// We look for 3 kinds of patterns here:
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// or with G0 or 0
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// add with G0 or 0
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// fmovs or FpMOVD (pseudo double move).
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if (MI.getOpcode() == SP::ORrr || MI.getOpcode() == SP::ADDrr) {
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if (MI.getOperand(1).getReg() == SP::G0) {
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DstReg = MI.getOperand(0).getReg();
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SrcReg = MI.getOperand(2).getReg();
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return true;
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} else if (MI.getOperand(2).getReg() == SP::G0) {
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DstReg = MI.getOperand(0).getReg();
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SrcReg = MI.getOperand(1).getReg();
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return true;
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}
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} else if ((MI.getOpcode() == SP::ORri || MI.getOpcode() == SP::ADDri) &&
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isZeroImm(MI.getOperand(2)) && MI.getOperand(1).isReg()) {
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DstReg = MI.getOperand(0).getReg();
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SrcReg = MI.getOperand(1).getReg();
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return true;
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} else if (MI.getOpcode() == SP::FMOVS || MI.getOpcode() == SP::FpMOVD ||
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MI.getOpcode() == SP::FMOVD) {
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SrcReg = MI.getOperand(1).getReg();
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DstReg = MI.getOperand(0).getReg();
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return true;
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}
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return false;
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}
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/// isLoadFromStackSlot - If the specified machine instruction is a direct
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/// load from a stack slot, return the virtual or physical register number of
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/// the destination along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than loading from the stack slot.
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unsigned SparcInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
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int &FrameIndex) const {
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if (MI->getOpcode() == SP::LDri ||
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MI->getOpcode() == SP::LDFri ||
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MI->getOpcode() == SP::LDDFri) {
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if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
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MI->getOperand(2).getImm() == 0) {
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FrameIndex = MI->getOperand(1).getIndex();
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return MI->getOperand(0).getReg();
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}
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}
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return 0;
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}
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/// isStoreToStackSlot - If the specified machine instruction is a direct
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/// store to a stack slot, return the virtual or physical register number of
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/// the source reg along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than storing to the stack slot.
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unsigned SparcInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
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int &FrameIndex) const {
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if (MI->getOpcode() == SP::STri ||
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MI->getOpcode() == SP::STFri ||
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MI->getOpcode() == SP::STDFri) {
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if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
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MI->getOperand(1).getImm() == 0) {
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FrameIndex = MI->getOperand(0).getIndex();
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return MI->getOperand(2).getReg();
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}
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}
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return 0;
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}
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unsigned
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SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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DebugLoc DL)const{
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// Can only insert uncond branches so far.
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assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
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BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB);
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return 1;
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}
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void SparcInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const {
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if (SP::IntRegsRegClass.contains(DestReg, SrcReg))
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BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0)
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.addReg(SrcReg, getKillRegState(KillSrc));
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else if (SP::FPRegsRegClass.contains(DestReg, SrcReg))
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BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg))
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BuildMI(MBB, I, DL, get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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else
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llvm_unreachable("Impossible reg-to-reg copy");
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}
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void SparcInstrInfo::
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storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned SrcReg, bool isKill, int FI,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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// On the order of operands here: think "[FrameIdx + 0] = SrcReg".
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if (RC == SP::IntRegsRegisterClass)
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BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0)
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.addReg(SrcReg, getKillRegState(isKill));
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else if (RC == SP::FPRegsRegisterClass)
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BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0)
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.addReg(SrcReg, getKillRegState(isKill));
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else if (RC == SP::DFPRegsRegisterClass)
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BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0)
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.addReg(SrcReg, getKillRegState(isKill));
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else
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llvm_unreachable("Can't store this register to stack slot");
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}
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void SparcInstrInfo::
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loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned DestReg, int FI,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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if (RC == SP::IntRegsRegisterClass)
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BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0);
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else if (RC == SP::FPRegsRegisterClass)
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BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0);
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else if (RC == SP::DFPRegsRegisterClass)
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BuildMI(MBB, I, DL, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0);
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else
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llvm_unreachable("Can't load this register from stack slot");
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}
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unsigned SparcInstrInfo::getGlobalBaseReg(MachineFunction *MF) const
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{
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SparcMachineFunctionInfo *SparcFI = MF->getInfo<SparcMachineFunctionInfo>();
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unsigned GlobalBaseReg = SparcFI->getGlobalBaseReg();
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if (GlobalBaseReg != 0)
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return GlobalBaseReg;
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// Insert the set of GlobalBaseReg into the first MBB of the function
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MachineBasicBlock &FirstMBB = MF->front();
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MachineBasicBlock::iterator MBBI = FirstMBB.begin();
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MachineRegisterInfo &RegInfo = MF->getRegInfo();
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GlobalBaseReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
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DebugLoc dl;
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BuildMI(FirstMBB, MBBI, dl, get(SP::GETPCX), GlobalBaseReg);
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SparcFI->setGlobalBaseReg(GlobalBaseReg);
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return GlobalBaseReg;
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}
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