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llvm-6502/test/CodeGen/Hexagon
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Jyotsna Verma b6716187ca Hexagon: Add support to lower block address. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176637 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-07 19:10:28 +00:00
..
absaddr-store.ll
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adde.ll
Hexagon: Expand addc, adde, subc and sube.
2013-03-05 19:04:47 +00:00
args.ll
Hexagon: Add encoding bits to the TFR64 instructions.
2013-03-05 18:42:28 +00:00
block-addr.ll
Hexagon: Add support to lower block address.
2013-03-07 19:10:28 +00:00
cext-check.ll
Hexagon: Move HexagonMCInst.h to MCTargetDesc/HexagonMCInst.h.
2013-02-20 16:13:27 +00:00
cext-valid-packet1.ll
Hexagon: Add constant extender support framework.
2013-03-01 17:37:13 +00:00
cext-valid-packet2.ll
Hexagon: Add constant extender support framework.
2013-03-01 17:37:13 +00:00
cmp_pred_reg.ll
Hexagon: Use TFR_cond with cmpb.[eq,gt,gtu] to handle
2013-02-05 19:20:45 +00:00
cmp_pred.ll
Hexagon: Use TFR_cond with cmpb.[eq,gt,gtu] to handle
2013-02-05 19:20:45 +00:00
cmp-to-genreg.ll
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cmp-to-predreg.ll
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cmpb_pred.ll
Hexagon: Use TFR_cond with cmpb.[eq,gt,gtu] to handle
2013-02-05 19:20:45 +00:00
combine_ir.ll
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combine.ll
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convertdptoint.ll
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convertdptoll.ll
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convertsptoint.ll
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convertsptoll.ll
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ctlz-cttz-ctpop.ll
Hexagon: Expand cttz, ctlz, and ctpop for now.
2013-02-21 19:39:40 +00:00
dadd.ll
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dmul.ll
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double.ll
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doubleconvert-ieee-rnd-near.ll
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dsub.ll
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dualstore.ll
Hexagon: Add encoding bits to the TFR64 instructions.
2013-03-05 18:42:28 +00:00
fadd.ll
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fcmp.ll
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float.ll
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floatconvert-ieee-rnd-near.ll
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fmul.ll
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frame.ll
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fsub.ll
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fusedandshift.ll
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gp-plus-offset-load.ll
Hexagon: Use absolute addressing mode loads/stores for global+offset
2013-02-13 21:38:46 +00:00
gp-plus-offset-store.ll
Hexagon: Use absolute addressing mode loads/stores for global+offset
2013-02-13 21:38:46 +00:00
hwloop-cleanup.ll
Extend Hexagon hardware loop generation to handle various additional cases:
2013-02-11 21:37:55 +00:00
hwloop-const.ll
Extend Hexagon hardware loop generation to handle various additional cases:
2013-02-11 21:37:55 +00:00
hwloop-dbg.ll
Extend Hexagon hardware loop generation to handle various additional cases:
2013-02-11 21:37:55 +00:00
hwloop-le.ll
Extend Hexagon hardware loop generation to handle various additional cases:
2013-02-11 21:37:55 +00:00
hwloop-lt1.ll
Extend Hexagon hardware loop generation to handle various additional cases:
2013-02-11 21:37:55 +00:00
hwloop-lt.ll
Extend Hexagon hardware loop generation to handle various additional cases:
2013-02-11 21:37:55 +00:00
hwloop-ne.ll
Extend Hexagon hardware loop generation to handle various additional cases:
2013-02-11 21:37:55 +00:00
idxload-with-zero-offset.ll
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indirect-br.ll
Hexagon: Add support to lower block address.
2013-03-07 19:10:28 +00:00
lit.local.cfg
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macint.ll
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mpy.ll
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newvaluejump2.ll
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newvaluejump.ll
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newvaluestore.ll
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opt-fabs.ll
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opt-fneg.ll
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postinc-load.ll
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postinc-store.ll
Hexagon: Add testcase for post-increment store instructions.
2013-02-05 18:23:51 +00:00
pred-absolute-store.ll
Hexagon: Add support to generate predicated absolute addressing mode
2013-02-12 16:06:23 +00:00
predicate-copy.ll
Hexagon: add support for predicate-GPR copies.
2013-02-13 22:56:34 +00:00
remove_lsr.ll
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simpletailcall.ll
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static.ll
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struct_args_large.ll
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struct_args.ll
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sube.ll
Hexagon: Expand addc, adde, subc and sube.
2013-03-05 19:04:47 +00:00
vaddh.ll
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validate-offset.ll
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