mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-11-03 14:21:30 +00:00
c9403659a9
code can do calling-convention queries. This obviates OutputArgReg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107786 91177308-0d34-0410-b5e6-96231b3b80d8
139 lines
5.0 KiB
C++
139 lines
5.0 KiB
C++
//===-- AlphaISelLowering.h - Alpha DAG Lowering Interface ------*- C++ -*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This file defines the interfaces that Alpha uses to lower LLVM code into a
|
|
// selection DAG.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#ifndef LLVM_TARGET_ALPHA_ALPHAISELLOWERING_H
|
|
#define LLVM_TARGET_ALPHA_ALPHAISELLOWERING_H
|
|
|
|
#include "llvm/ADT/VectorExtras.h"
|
|
#include "llvm/Target/TargetLowering.h"
|
|
#include "llvm/CodeGen/SelectionDAG.h"
|
|
#include "Alpha.h"
|
|
|
|
namespace llvm {
|
|
|
|
namespace AlphaISD {
|
|
enum NodeType {
|
|
// Start the numbering where the builting ops and target ops leave off.
|
|
FIRST_NUMBER = ISD::BUILTIN_OP_END,
|
|
//These corrospond to the identical Instruction
|
|
CVTQT_, CVTQS_, CVTTQ_,
|
|
|
|
/// GPRelHi/GPRelLo - These represent the high and low 16-bit
|
|
/// parts of a global address respectively.
|
|
GPRelHi, GPRelLo,
|
|
|
|
/// RetLit - Literal Relocation of a Global
|
|
RelLit,
|
|
|
|
/// GlobalRetAddr - used to restore the return address
|
|
GlobalRetAddr,
|
|
|
|
/// CALL - Normal call.
|
|
CALL,
|
|
|
|
/// DIVCALL - used for special library calls for div and rem
|
|
DivCall,
|
|
|
|
/// return flag operand
|
|
RET_FLAG,
|
|
|
|
/// CHAIN = COND_BRANCH CHAIN, OPC, (G|F)PRC, DESTBB [, INFLAG] - This
|
|
/// corresponds to the COND_BRANCH pseudo instruction.
|
|
/// *PRC is the input register to compare to zero,
|
|
/// OPC is the branch opcode to use (e.g. Alpha::BEQ),
|
|
/// DESTBB is the destination block to branch to, and INFLAG is
|
|
/// an optional input flag argument.
|
|
COND_BRANCH_I, COND_BRANCH_F
|
|
|
|
};
|
|
}
|
|
|
|
class AlphaTargetLowering : public TargetLowering {
|
|
public:
|
|
explicit AlphaTargetLowering(TargetMachine &TM);
|
|
|
|
/// getSetCCResultType - Get the SETCC result ValueType
|
|
virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const;
|
|
|
|
/// LowerOperation - Provide custom lowering hooks for some operations.
|
|
///
|
|
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
/// ReplaceNodeResults - Replace the results of node with an illegal result
|
|
/// type with new values built out of custom code.
|
|
///
|
|
virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
|
|
SelectionDAG &DAG) const;
|
|
|
|
// Friendly names for dumps
|
|
const char *getTargetNodeName(unsigned Opcode) const;
|
|
|
|
SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
|
|
CallingConv::ID CallConv, bool isVarArg,
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
DebugLoc dl, SelectionDAG &DAG,
|
|
SmallVectorImpl<SDValue> &InVals) const;
|
|
|
|
ConstraintType getConstraintType(const std::string &Constraint) const;
|
|
|
|
std::vector<unsigned>
|
|
getRegClassForInlineAsmConstraint(const std::string &Constraint,
|
|
EVT VT) const;
|
|
|
|
MachineBasicBlock *
|
|
EmitInstrWithCustomInserter(MachineInstr *MI,
|
|
MachineBasicBlock *BB) const;
|
|
|
|
virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
|
|
|
|
/// getFunctionAlignment - Return the Log2 alignment of this function.
|
|
virtual unsigned getFunctionAlignment(const Function *F) const;
|
|
|
|
/// isFPImmLegal - Returns true if the target can instruction select the
|
|
/// specified FP immediate natively. If false, the legalizer will
|
|
/// materialize the FP immediate as a load from a constant pool.
|
|
virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
|
|
|
|
private:
|
|
// Helpers for custom lowering.
|
|
void LowerVAARG(SDNode *N, SDValue &Chain, SDValue &DataPtr,
|
|
SelectionDAG &DAG) const;
|
|
|
|
virtual SDValue
|
|
LowerFormalArguments(SDValue Chain,
|
|
CallingConv::ID CallConv, bool isVarArg,
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
DebugLoc dl, SelectionDAG &DAG,
|
|
SmallVectorImpl<SDValue> &InVals) const;
|
|
|
|
virtual SDValue
|
|
LowerCall(SDValue Chain, SDValue Callee,
|
|
CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
|
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
|
const SmallVectorImpl<SDValue> &OutVals,
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
DebugLoc dl, SelectionDAG &DAG,
|
|
SmallVectorImpl<SDValue> &InVals) const;
|
|
|
|
virtual SDValue
|
|
LowerReturn(SDValue Chain,
|
|
CallingConv::ID CallConv, bool isVarArg,
|
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
|
const SmallVectorImpl<SDValue> &OutVals,
|
|
DebugLoc dl, SelectionDAG &DAG) const;
|
|
};
|
|
}
|
|
|
|
#endif // LLVM_TARGET_ALPHA_ALPHAISELLOWERING_H
|