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https://github.com/c64scene-ar/llvm-6502.git
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f09378397e
per-function subtarget. Currently, code-gen passes the default or generic subtarget to the constructors of MCInstPrinter subclasses (see LLVMTargetMachine::addPassesToEmitFile), which enables some targets (AArch64, ARM, and X86) to change their instprinter's behavior based on the subtarget feature bits. Since the backend can now use different subtargets for each function, instprinter has to be changed to use the per-function subtarget rather than the default subtarget. This patch takes the first step towards enabling instprinter to change its behavior based on the per-function subtarget. It adds a bit "PassSubtarget" to AsmWriter which tells table-gen to pass a reference to MCSubtargetInfo to the various print methods table-gen auto-generates. I will follow up with changes to instprinters of AArch64, ARM, and X86. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233411 91177308-0d34-0410-b5e6-96231b3b80d8
88 lines
2.4 KiB
C++
88 lines
2.4 KiB
C++
//===-- XCoreInstPrinter.cpp - Convert XCore MCInst to assembly syntax ----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This class prints an XCore MCInst to a .s file.
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//
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//===----------------------------------------------------------------------===//
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#include "XCoreInstPrinter.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "asm-printer"
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#include "XCoreGenAsmWriter.inc"
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void XCoreInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
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OS << StringRef(getRegisterName(RegNo)).lower();
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}
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void XCoreInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
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StringRef Annot, const MCSubtargetInfo &STI) {
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printInstruction(MI, O);
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printAnnotation(O, Annot);
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}
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void XCoreInstPrinter::
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printInlineJT(const MCInst *MI, int opNum, raw_ostream &O) {
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report_fatal_error("can't handle InlineJT");
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}
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void XCoreInstPrinter::
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printInlineJT32(const MCInst *MI, int opNum, raw_ostream &O) {
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report_fatal_error("can't handle InlineJT32");
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}
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static void printExpr(const MCExpr *Expr, raw_ostream &OS) {
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int Offset = 0;
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const MCSymbolRefExpr *SRE;
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if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(Expr)) {
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SRE = dyn_cast<MCSymbolRefExpr>(BE->getLHS());
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(BE->getRHS());
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assert(SRE && CE && "Binary expression must be sym+const.");
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Offset = CE->getValue();
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} else {
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SRE = dyn_cast<MCSymbolRefExpr>(Expr);
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assert(SRE && "Unexpected MCExpr type.");
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}
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assert(SRE->getKind() == MCSymbolRefExpr::VK_None);
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OS << SRE->getSymbol();
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if (Offset) {
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if (Offset > 0)
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OS << '+';
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OS << Offset;
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}
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}
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void XCoreInstPrinter::
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printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
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const MCOperand &Op = MI->getOperand(OpNo);
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if (Op.isReg()) {
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printRegName(O, Op.getReg());
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return;
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}
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if (Op.isImm()) {
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O << Op.getImm();
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return;
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}
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assert(Op.isExpr() && "unknown operand kind in printOperand");
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printExpr(Op.getExpr(), O);
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}
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