Vincent Lejeune e3111964a0 R600/SI: Use MULADD_IEEE/V_MAD_F32 instruction for mad pattern ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175446 91177308-0d34-0410-b5e6-96231b3b80d8

2013-02-18 14:11:28 +00:00

..

AArch64

AArch64: remove ConstantIsland pass & put literals in separate section.

2013-02-15 09:33:43 +00:00

ARM

Re-apply r175088 for bug fix 13622: Add paired register support for

2013-02-14 18:10:21 +00:00

CPP

…

Generic

For inline asm:

2013-01-11 18:12:39 +00:00

Hexagon

Hexagon: add support for predicate-GPR copies.

2013-02-13 22:56:34 +00:00

MBlaze

…

Mips

Expand macro/pseudo instructions BtnezT8SltX16 and BtnezT8SltuX16.

2013-02-18 05:43:03 +00:00

MSP430

Add support for varargs functions for msp430.

2012-11-21 17:28:27 +00:00

NVPTX

[NVPTX] Disable vector registers

2013-02-12 14:18:49 +00:00

PowerPC

DAGCombiner: Constant folding around pre-increment loads/stores

2013-02-08 21:35:47 +00:00

R600

R600/SI: Use MULADD_IEEE/V_MAD_F32 instruction for mad pattern

2013-02-18 14:11:28 +00:00

SI

Add R600 backend

2012-12-11 21:25:42 +00:00

SPARC

Use TargetTransformInfo to control switch-to-lookup table transformation

2012-10-30 11:23:25 +00:00

Thumb

Use the 'count' attribute to calculate the upper bound of an array.

2012-12-04 21:34:03 +00:00

Thumb2

FileCheck-ify some grep tests

2013-01-25 22:11:46 +00:00

X86

Force a cpu for test. It failed on atom due to different scheduling decisions.

2013-02-17 18:26:11 +00:00

XCore

Fix handling of aliases to functions.

2012-11-16 21:12:38 +00:00