Tom Stellard b89a467559 R600/SI: Handle REG_SEQUENCE in fitsRegClass() ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183134 91177308-0d34-0410-b5e6-96231b3b80d8

2013-06-03 17:39:54 +00:00

..

InstPrinter

Move passes from namespace llvm into anonymous namespaces. Sort includes while there.

2013-05-23 17:10:37 +00:00

MCTargetDesc

R600: Hide symbols of implementation details.

2013-05-23 15:43:05 +00:00

TargetInfo

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AMDGPU.h

R600: Improve texture handling

2013-05-17 16:50:20 +00:00

AMDGPU.td

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AMDGPUAsmPrinter.cpp

Move passes from namespace llvm into anonymous namespaces. Sort includes while there.

2013-05-23 17:10:37 +00:00

AMDGPUAsmPrinter.h

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AMDGPUCallingConv.td

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AMDGPUConvertToISA.cpp

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AMDGPUFrameLowering.cpp

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AMDGPUFrameLowering.h

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AMDGPUIndirectAddressing.cpp

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AMDGPUInstrInfo.cpp

R600: Hide symbols of implementation details.

2013-05-23 15:43:05 +00:00

AMDGPUInstrInfo.h

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AMDGPUInstrInfo.td

Create an FPOW SDNode opcode def in the target independent .td file rather than in a specific backend.

2013-05-22 06:36:09 +00:00

AMDGPUInstructions.td

R600/SI: Add support for global loads

2013-06-03 17:39:43 +00:00

AMDGPUIntrinsics.td

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AMDGPUISelLowering.cpp

Track IR ordering of SelectionDAG nodes 2/4.

2013-05-25 02:42:55 +00:00

AMDGPUISelLowering.h

R600/SI: Rework MUBUF store instructions

2013-06-03 17:39:37 +00:00

AMDGPUMachineFunction.cpp

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AMDGPUMachineFunction.h

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AMDGPUMCInstLower.cpp

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AMDGPUMCInstLower.h

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AMDGPURegisterInfo.cpp

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AMDGPURegisterInfo.h

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AMDGPURegisterInfo.td

Make SubRegIndex size mandatory, following r183020.

2013-05-31 23:45:26 +00:00

AMDGPUStructurizeCFG.cpp

Move passes from namespace llvm into anonymous namespaces. Sort includes while there.

2013-05-23 17:10:37 +00:00

AMDGPUSubtarget.cpp

Temporary fix to get rid of gcc warning.

2013-05-29 07:32:08 +00:00

AMDGPUSubtarget.h

R600: Factorize Fetch size limit inside AMDGPUSubTarget

2013-05-17 16:49:55 +00:00

AMDGPUTargetMachine.cpp

Fix a leak on the r600 backend.

2013-05-23 03:31:47 +00:00

AMDGPUTargetMachine.h

Fix a leak on the r600 backend.

2013-05-23 03:31:47 +00:00

AMDIL7XXDevice.cpp

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AMDIL7XXDevice.h

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AMDIL.h

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AMDILBase.td

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AMDILCFGStructurizer.cpp

R600: Hide symbols of implementation details.

2013-05-23 15:43:05 +00:00

AMDILDevice.cpp

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AMDILDevice.h

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AMDILDeviceInfo.cpp

R600/SI: Add processor type for Hainan asic

2013-05-14 14:42:56 +00:00

AMDILDeviceInfo.h

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AMDILDevices.h

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AMDILEvergreenDevice.cpp

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AMDILEvergreenDevice.h

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AMDILInstrInfo.td

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AMDILIntrinsicInfo.cpp

Check that a function starts with llvm. before using GET_FUNCTION_RECOGNIZER.

2013-05-22 14:57:42 +00:00

AMDILIntrinsicInfo.h

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AMDILIntrinsics.td

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AMDILISelDAGToDAG.cpp

R600/SI: Fixup CopyToReg register class in PostprocessISelDAG()

2013-06-03 17:39:46 +00:00

AMDILISelLowering.cpp

Track IR ordering of SelectionDAG nodes 2/4.

2013-05-25 02:42:55 +00:00

AMDILNIDevice.cpp

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AMDILNIDevice.h

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AMDILRegisterInfo.td

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AMDILSIDevice.cpp

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AMDILSIDevice.h

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CMakeLists.txt

R600: Improve texture handling

2013-05-17 16:50:20 +00:00

LLVMBuild.txt

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Makefile

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Processors.td

R600/SI: Add processor type for Hainan asic

2013-05-14 14:42:56 +00:00

R600ControlFlowFinalizer.cpp

R600: CALL_FS consumes a stack size entry

2013-06-03 15:44:42 +00:00

R600Defines.h

R600: Relax some vector constraints on Dot4.

2013-05-17 16:50:32 +00:00

R600EmitClauseMarkers.cpp

Move passes from namespace llvm into anonymous namespaces. Sort includes while there.

2013-05-23 17:10:37 +00:00

R600ExpandSpecialInstrs.cpp

Fix warning in non-assert build.

2013-05-22 01:29:38 +00:00

R600InstrInfo.cpp

Move passes from namespace llvm into anonymous namespaces. Sort includes while there.

2013-05-23 17:10:37 +00:00

R600InstrInfo.h

R600: Relax some vector constraints on Dot4.

2013-05-17 16:50:32 +00:00

R600Instructions.td

R600: Constraints input regs of interp_xy,_zw

2013-06-03 15:44:16 +00:00

R600Intrinsics.td

R600: Improve texture handling

2013-05-17 16:50:20 +00:00

R600ISelLowering.cpp

R600: Constraints input regs of interp_xy,_zw

2013-06-03 15:44:16 +00:00

R600ISelLowering.h

Track IR ordering of SelectionDAG nodes 2/4.

2013-05-25 02:42:55 +00:00

R600MachineFunctionInfo.cpp

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R600MachineFunctionInfo.h

Move passes from namespace llvm into anonymous namespaces. Sort includes while there.

2013-05-23 17:10:37 +00:00

R600MachineScheduler.cpp

Move passes from namespace llvm into anonymous namespaces. Sort includes while there.

2013-05-23 17:10:37 +00:00

R600MachineScheduler.h

Move passes from namespace llvm into anonymous namespaces. Sort includes while there.

2013-05-23 17:10:37 +00:00

R600Packetizer.cpp

R600: 3 op instructions have no write bit but the result are store in PV

2013-06-03 15:56:12 +00:00

R600RegisterInfo.cpp

R600: Use bottom up scheduling algorithm

2013-05-17 16:50:56 +00:00

R600RegisterInfo.h

R600: Use bottom up scheduling algorithm

2013-05-17 16:50:56 +00:00

R600RegisterInfo.td

R600: use capital letter for PV channel

2013-06-03 15:44:35 +00:00

R600Schedule.td

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R600TextureIntrinsicsReplacer.cpp

Move passes from namespace llvm into anonymous namespaces. Sort includes while there.

2013-05-23 17:10:37 +00:00

SIAnnotateControlFlow.cpp

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SIDefines.h

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SIInsertWaits.cpp

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SIInstrFormats.td

R600/SI: Use the same names for VOP3 operands and encoding fields

2013-05-20 15:02:08 +00:00

SIInstrInfo.cpp

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SIInstrInfo.h

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SIInstrInfo.td

R600/SI: Add support for global loads

2013-06-03 17:39:43 +00:00

SIInstructions.td

R600/SI: Add support for global loads

2013-06-03 17:39:43 +00:00

SIIntrinsics.td

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SIISelLowering.cpp

R600/SI: Handle REG_SEQUENCE in fitsRegClass()

2013-06-03 17:39:54 +00:00

SIISelLowering.h

R600/SI: Rework MUBUF store instructions

2013-06-03 17:39:37 +00:00

SILowerControlFlow.cpp

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SIMachineFunctionInfo.cpp

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SIMachineFunctionInfo.h

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SIRegisterInfo.cpp

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SIRegisterInfo.h

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SIRegisterInfo.td

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SISchedule.td

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