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	utils/sort_includes.py. I clearly haven't done this in a while, so more changed than usual. This even uncovered a missing include from the InstrProf library that I've added. No functionality changed here, just mechanical cleanup of the include order. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225974 91177308-0d34-0410-b5e6-96231b3b80d8
		
			
				
	
	
		
			193 lines
		
	
	
		
			6.4 KiB
		
	
	
	
		
			C++
		
	
	
	
	
	
			
		
		
	
	
			193 lines
		
	
	
		
			6.4 KiB
		
	
	
	
		
			C++
		
	
	
	
	
	
| //===-- LiveRegMatrix.cpp - Track register interference -------------------===//
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| //
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| //                     The LLVM Compiler Infrastructure
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| //
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| // This file is distributed under the University of Illinois Open Source
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| // License. See LICENSE.TXT for details.
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| //
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| //===----------------------------------------------------------------------===//
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| //
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| // This file defines the LiveRegMatrix analysis pass.
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| //
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| //===----------------------------------------------------------------------===//
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| 
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| #include "llvm/CodeGen/LiveRegMatrix.h"
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| #include "RegisterCoalescer.h"
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| #include "llvm/ADT/Statistic.h"
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| #include "llvm/CodeGen/LiveIntervalAnalysis.h"
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| #include "llvm/CodeGen/MachineRegisterInfo.h"
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| #include "llvm/CodeGen/VirtRegMap.h"
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| #include "llvm/Support/Debug.h"
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| #include "llvm/Support/Format.h"
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| #include "llvm/Support/raw_ostream.h"
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| #include "llvm/Target/TargetRegisterInfo.h"
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| 
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| using namespace llvm;
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| 
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| #define DEBUG_TYPE "regalloc"
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| 
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| STATISTIC(NumAssigned   , "Number of registers assigned");
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| STATISTIC(NumUnassigned , "Number of registers unassigned");
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| 
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| char LiveRegMatrix::ID = 0;
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| INITIALIZE_PASS_BEGIN(LiveRegMatrix, "liveregmatrix",
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|                       "Live Register Matrix", false, false)
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| INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
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| INITIALIZE_PASS_DEPENDENCY(VirtRegMap)
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| INITIALIZE_PASS_END(LiveRegMatrix, "liveregmatrix",
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|                     "Live Register Matrix", false, false)
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| 
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| LiveRegMatrix::LiveRegMatrix() : MachineFunctionPass(ID),
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|   UserTag(0), RegMaskTag(0), RegMaskVirtReg(0) {}
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| 
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| void LiveRegMatrix::getAnalysisUsage(AnalysisUsage &AU) const {
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|   AU.setPreservesAll();
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|   AU.addRequiredTransitive<LiveIntervals>();
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|   AU.addRequiredTransitive<VirtRegMap>();
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|   MachineFunctionPass::getAnalysisUsage(AU);
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| }
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| 
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| bool LiveRegMatrix::runOnMachineFunction(MachineFunction &MF) {
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|   TRI = MF.getSubtarget().getRegisterInfo();
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|   MRI = &MF.getRegInfo();
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|   LIS = &getAnalysis<LiveIntervals>();
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|   VRM = &getAnalysis<VirtRegMap>();
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| 
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|   unsigned NumRegUnits = TRI->getNumRegUnits();
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|   if (NumRegUnits != Matrix.size())
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|     Queries.reset(new LiveIntervalUnion::Query[NumRegUnits]);
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|   Matrix.init(LIUAlloc, NumRegUnits);
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| 
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|   // Make sure no stale queries get reused.
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|   invalidateVirtRegs();
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|   return false;
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| }
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| 
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| void LiveRegMatrix::releaseMemory() {
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|   for (unsigned i = 0, e = Matrix.size(); i != e; ++i) {
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|     Matrix[i].clear();
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|     // No need to clear Queries here, since LiveIntervalUnion::Query doesn't
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|     // have anything important to clear and LiveRegMatrix's runOnFunction()
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|     // does a std::unique_ptr::reset anyways.
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|   }
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| }
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| 
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| template<typename Callable>
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| bool foreachUnit(const TargetRegisterInfo *TRI, LiveInterval &VRegInterval,
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|                  unsigned PhysReg, Callable Func) {
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|   if (VRegInterval.hasSubRanges()) {
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|     for (MCRegUnitMaskIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
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|       unsigned Unit = (*Units).first;
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|       unsigned Mask = (*Units).second;
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|       for (LiveInterval::SubRange &S : VRegInterval.subranges()) {
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|         if (S.LaneMask & Mask) {
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|           if (Func(Unit, S))
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|             return true;
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|           break;
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|         }
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|       }
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|     }
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|   } else {
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|     for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
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|       if (Func(*Units, VRegInterval))
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|         return true;
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|     }
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|   }
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|   return false;
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| }
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| 
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| void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) {
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|   DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI)
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|                << " to " << PrintReg(PhysReg, TRI) << ':');
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|   assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment");
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|   VRM->assignVirt2Phys(VirtReg.reg, PhysReg);
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|   MRI->setPhysRegUsed(PhysReg);
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| 
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|   foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit,
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|                                          const LiveRange &Range) {
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|     DEBUG(dbgs() << ' ' << PrintRegUnit(Unit, TRI) << ' ' << Range);
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|     Matrix[Unit].unify(VirtReg, Range);
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|     return false;
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|   });
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| 
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|   ++NumAssigned;
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|   DEBUG(dbgs() << '\n');
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| }
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| 
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| void LiveRegMatrix::unassign(LiveInterval &VirtReg) {
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|   unsigned PhysReg = VRM->getPhys(VirtReg.reg);
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|   DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg.reg, TRI)
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|                << " from " << PrintReg(PhysReg, TRI) << ':');
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|   VRM->clearVirt(VirtReg.reg);
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| 
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|   foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit,
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|                                          const LiveRange &Range) {
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|     DEBUG(dbgs() << ' ' << PrintRegUnit(Unit, TRI));
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|     Matrix[Unit].extract(VirtReg, Range);
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|     return false;
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|   });
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| 
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|   ++NumUnassigned;
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|   DEBUG(dbgs() << '\n');
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| }
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| 
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| bool LiveRegMatrix::checkRegMaskInterference(LiveInterval &VirtReg,
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|                                              unsigned PhysReg) {
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|   // Check if the cached information is valid.
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|   // The same BitVector can be reused for all PhysRegs.
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|   // We could cache multiple VirtRegs if it becomes necessary.
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|   if (RegMaskVirtReg != VirtReg.reg || RegMaskTag != UserTag) {
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|     RegMaskVirtReg = VirtReg.reg;
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|     RegMaskTag = UserTag;
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|     RegMaskUsable.clear();
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|     LIS->checkRegMaskInterference(VirtReg, RegMaskUsable);
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|   }
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| 
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|   // The BitVector is indexed by PhysReg, not register unit.
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|   // Regmask interference is more fine grained than regunits.
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|   // For example, a Win64 call can clobber %ymm8 yet preserve %xmm8.
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|   return !RegMaskUsable.empty() && (!PhysReg || !RegMaskUsable.test(PhysReg));
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| }
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| 
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| bool LiveRegMatrix::checkRegUnitInterference(LiveInterval &VirtReg,
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|                                              unsigned PhysReg) {
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|   if (VirtReg.empty())
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|     return false;
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|   CoalescerPair CP(VirtReg.reg, PhysReg, *TRI);
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| 
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|   bool Result = foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit,
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|                                                        const LiveRange &Range) {
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|     const LiveRange &UnitRange = LIS->getRegUnit(Unit);
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|     return Range.overlaps(UnitRange, CP, *LIS->getSlotIndexes());
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|   });
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|   return Result;
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| }
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| 
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| LiveIntervalUnion::Query &LiveRegMatrix::query(LiveInterval &VirtReg,
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|                                                unsigned RegUnit) {
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|   LiveIntervalUnion::Query &Q = Queries[RegUnit];
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|   Q.init(UserTag, &VirtReg, &Matrix[RegUnit]);
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|   return Q;
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| }
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| 
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| LiveRegMatrix::InterferenceKind
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| LiveRegMatrix::checkInterference(LiveInterval &VirtReg, unsigned PhysReg) {
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|   if (VirtReg.empty())
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|     return IK_Free;
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| 
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|   // Regmask interference is the fastest check.
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|   if (checkRegMaskInterference(VirtReg, PhysReg))
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|     return IK_RegMask;
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| 
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|   // Check for fixed interference.
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|   if (checkRegUnitInterference(VirtReg, PhysReg))
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|     return IK_RegUnit;
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| 
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|   // Check the matrix for virtual register interference.
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|   for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units)
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|     if (query(VirtReg, *Units).checkInterference())
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|       return IK_VirtReg;
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| 
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|   return IK_Free;
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| }
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