Evan Cheng b9803a8fa6 - Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relative ... load of a GV from constantpool and then add pc. It allows the code sequence to be rematerializable so it would be hoisted by machine licm. - Add a late pass to break these pseudo instructions into a number of real instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm to this pass. This is done before post regalloc scheduling to allow the scheduler to proper schedule these instructions. It also allow them to be if-converted and shrunk by later passes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86304 91177308-0d34-0410-b5e6-96231b3b80d8		2009-11-06 23:52:48 +00:00
..
Analysis	Revert r86077 because it caused crashes in 179.art and 175.vpr on ARM	2009-11-06 01:33:24 +00:00
Archive
Assembler
Bindings/Ocaml
Bitcode
BugPoint
CodeGen	- Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relative	2009-11-06 23:52:48 +00:00
DebugInfo	fix typo	2009-11-06 20:10:46 +00:00
ExecutionEngine
Feature	add bitcode reader support for blockaddress. We can now fully	2009-10-28 05:53:48 +00:00
FrontendAda
FrontendC
FrontendC++	turn IPSCCP back on by default, try #3 or 4? Woo.	2009-11-03 19:35:13 +00:00
FrontendFortran
FrontendObjC
FrontendObjC++
Integer
lib
Linker
LLVMC
MC
Other
Scripts
TableGen
Transforms	Fix a problem discovered on self host.	2009-11-06 19:21:48 +00:00
Unit
Verifier
CMakeLists.txt
lit.cfg	Add missing substitution for %llvmgcc_only.	2009-10-30 21:13:59 +00:00
lit.site.cfg.in
Makefile
Makefile.tests
site.exp.in
TestRunner.sh