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LLVM backend for 6502
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Jakob Stoklund Olesen babf0569e2 Teach TableGen to infer missing register classes. 
The set of register classes should be closed under sub-register
operations and intersections. That will allow the register allocator to
model combinations of constraints accurately.

This patch implements the easiest form of register class inference:  For
every register class, and for every sub-register SubIdx, the subset of
registers in RC that have a SubIdx sub-register should also be a register
class.

This does create some new register classes for the targets in the tree:

ARM gets a new QQQQPR_with_ssub_0.  This class was omitted from the .td
file on purpose because it only has two registers.  InstrEmitter and
RegisterCoalescer have safeguards against selecting too small register
classes, so it is harmless.

PowerPC gets a G8RC_with_sub_32 class because LR is not a sub_32
sub-register of LR8.  I think that might be an omission?

X86 puts RIP in the GR64 class, and since that register doesn't have
8-bit sub-registers, we get:

  GR64_with_sub_8bit
  GR64_TC_with_sub_8bit
  GR64_NOREX_with_sub_8bit
  GR64_TC_with_sub_8bit_hi

The various CodeGen classes have already been fixed so adding new
register classes should not affect compile time.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141084 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 15:28:49 +00:00
autoconf We're no longer going to bother supporting platforms that don't 2011-09-23 00:53:10 +00:00
bindings attempt to fix ocaml bindings: landing pads 2011-10-03 06:41:46 +00:00
cmake Rename LLVM_MULTITHREADED define and fix build without threads. 2011-09-19 20:43:23 +00:00
docs Remove last references to hotpatch. 2011-10-04 03:08:43 +00:00
examples Changed comments on foreign C++ exceptions (generated with type info 7), 2011-09-28 10:53:56 +00:00
include The product of two chrec's can always be represented as a chrec. 2011-10-04 06:51:26 +00:00
lib Teach PPCInstrInfo to handle sub-classes. 2011-10-04 15:28:47 +00:00
projects Fix a ton of comment typos found by codespell. Patch by 2011-04-15 05:18:47 +00:00
runtime Fix for warnings: ignoring return value of ‘write’, declared with attribute warn_unused_result. 2011-09-22 17:33:24 +00:00
test Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676. 2011-10-04 06:30:42 +00:00
tools Exclude libLLVMTableGen.a from the shared library 2011-10-04 00:30:34 +00:00
unittests The product of two chrec's can always be represented as a chrec. 2011-10-04 06:51:26 +00:00
utils Teach TableGen to infer missing register classes. 2011-10-04 15:28:49 +00:00
website
.gitignore Revert change made in .gitignore. 2011-09-24 01:37:58 +00:00
build-for-llvm-top.sh
CMakeLists.txt Move TableGen's parser and entry point into a library 2011-10-01 16:41:13 +00:00
configure We're no longer going to bother supporting platforms that don't 2011-09-23 00:53:10 +00:00
CREDITS.TXT Claimed. 2011-09-19 05:34:10 +00:00
LICENSE.TXT Happy new year. 2011-06-12 15:26:54 +00:00
llvm.spec.in
Makefile Move TableGen's parser and entry point into a library 2011-10-01 16:41:13 +00:00
Makefile.common
Makefile.config.in Remove the rest of the compiler checking from the top level configure 2011-09-21 00:53:42 +00:00
Makefile.rules More llvmc bits. Spotted by Benjamin on IRC. 2011-09-20 00:42:28 +00:00
ModuleInfo.txt
README.txt Test commit 2011-09-21 03:34:31 +00:00

README.txt 

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