Chad Rosier e5e674ba11 [fast-isel] Fallback to SelectionDAG isel if we require strict alignment for ...

non-aligned i32 loads/stores.
rdar://12304911

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164381 91177308-0d34-0410-b5e6-96231b3b80d8

2012-09-21 16:58:35 +00:00

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ARM

[fast-isel] Fallback to SelectionDAG isel if we require strict alignment for

2012-09-21 16:58:35 +00:00

CellSPU

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CPP

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Generic

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Hexagon

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MBlaze

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Mips

Handled unaligned load/stores properly in Mips16

2012-09-15 01:02:03 +00:00

MSP430

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NVPTX

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PowerPC

Specify cpu to get the correct instruction ordering. Remove XFAIL.

2012-09-20 14:59:42 +00:00

SPARC

Move load_to_switch.ll to test/CodeGen/SPARC/

2012-09-19 09:25:03 +00:00

Thumb

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Thumb2

Use vld1 / vst2 for unaligned v2f64 load / store. e.g. Use vld1.16 for 2-byte

2012-09-18 01:42:45 +00:00

X86

llvm/test/CodeGen/X86/pr5145.ll: Tweak expressions to match for darwin target.

2012-09-21 05:19:19 +00:00

XCore

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