mirror of
https://github.com/c64scene-ar/llvm-6502.git
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bc6fc20fcc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137071 91177308-0d34-0410-b5e6-96231b3b80d8
92 lines
3.8 KiB
ArmAsm
92 lines
3.8 KiB
ArmAsm
@ RUN: llvm-mc -triple=armv7-apple-darwin -show-encoding < %s | FileCheck %s
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.syntax unified
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.globl _func
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@ Check that the assembler can handle the documented syntax from the ARM ARM
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@ for loads and stores.
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_func:
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@ CHECK: _func
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@------------------------------------------------------------------------------
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@ LDR (immediate)
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@------------------------------------------------------------------------------
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ldr r5, [r7]
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ldr r6, [r3, #63]
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ldr r2, [r4, #4095]!
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ldr r1, [r2], #30
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ldr r3, [r1], #-30
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@ CHECK: ldr r5, [r7] @ encoding: [0x00,0x50,0x97,0xe5]
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@ CHECK: ldr r6, [r3, #63] @ encoding: [0x3f,0x60,0x93,0xe5]
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@ CHECK: ldr r2, [r4, #4095]! @ encoding: [0xff,0x2f,0xb4,0xe5]
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@ CHECK: ldr r1, [r2], #30 @ encoding: [0x1e,0x10,0x92,0xe4]
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@ CHECK: ldr r3, [r1], #-30 @ encoding: [0x1e,0x30,0x11,0xe4]
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@------------------------------------------------------------------------------
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@ FIXME: LDR (literal)
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@------------------------------------------------------------------------------
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@ label operands currently assert the show-encoding asm comment helper due
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@ to the use of non-contiguous bit ranges for fixups in ARM. Once that's
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@ cleaned up, we can write useful assembly testcases for these sorts of
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@ instructions.
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@------------------------------------------------------------------------------
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@ LDR (register)
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@------------------------------------------------------------------------------
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ldr r3, [r8, r1]
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ldr r2, [r5, -r3]
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ldr r1, [r5, r9]!
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ldr r6, [r7, -r8]!
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ldr r5, [r9], r2
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ldr r4, [r3], -r6
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ldr r3, [r8, -r2, lsl #15]
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ldr r1, [r5], r3, asr #15
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@ CHECK: ldr r3, [r8, r1] @ encoding: [0x01,0x30,0x98,0xe7]
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@ CHECK: ldr r2, [r5, -r3] @ encoding: [0x03,0x20,0x15,0xe7]
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@ CHECK: ldr r1, [r5, r9]! @ encoding: [0x09,0x10,0xb5,0xe7]
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@ CHECK: ldr r6, [r7, -r8]! @ encoding: [0x08,0x60,0x37,0xe7]
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@ CHECK: ldr r5, [r9], r2 @ encoding: [0x02,0x50,0x99,0xe6]
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@ CHECK: ldr r4, [r3], -r6 @ encoding: [0x06,0x40,0x13,0xe6]
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@ CHECK: ldr r3, [r8, -r2, lsl #15] @ encoding: [0x82,0x37,0x18,0xe7]
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@ CHECK: ldr r1, [r5], r3, asr #15 @ encoding: [0xc3,0x17,0x95,0xe6]
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@------------------------------------------------------------------------------
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@ LDRB (immediate)
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@------------------------------------------------------------------------------
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ldrb r3, [r8]
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ldrb r1, [sp, #63]
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ldrb r9, [r3, #4095]!
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ldrb r8, [r1], #22
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ldrb r2, [r7], #-19
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@ CHECK: ldrb r3, [r8] @ encoding: [0x00,0x30,0xd8,0xe5]
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@ CHECK: ldrb r1, [sp, #63] @ encoding: [0x3f,0x10,0xdd,0xe5]
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@ CHECK: ldrb r9, [r3, #4095]! @ encoding: [0xff,0x9f,0xf3,0xe5]
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@ CHECK: ldrb r8, [r1], #22 @ encoding: [0x16,0x80,0xd1,0xe4]
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@ CHECK: ldrb r2, [r7], #-19 @ encoding: [0x13,0x20,0x57,0xe4]
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@------------------------------------------------------------------------------
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@ LDRB (register)
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@------------------------------------------------------------------------------
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ldr r9, [r8, r5]
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ldr r1, [r5, -r1]
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ldr r3, [r5, r2]!
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ldr r6, [r9, -r3]!
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ldr r2, [r1], r4
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ldr r8, [r4], -r5
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ldr r7, [r12, -r1, lsl #15]
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ldr r5, [r2], r9, asr #15
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@ CHECK: ldr r9, [r8, r5] @ encoding: [0x05,0x90,0x98,0xe7]
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@ CHECK: ldr r1, [r5, -r1] @ encoding: [0x01,0x10,0x15,0xe7]
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@ CHECK: ldr r3, [r5, r2]! @ encoding: [0x02,0x30,0xb5,0xe7]
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@ CHECK: ldr r6, [r9, -r3]! @ encoding: [0x03,0x60,0x39,0xe7]
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@ CHECK: ldr r2, [r1], r4 @ encoding: [0x04,0x20,0x91,0xe6]
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@ CHECK: ldr r8, [r4], -r5 @ encoding: [0x05,0x80,0x14,0xe6]
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@ CHECK: ldr r7, [r12, -r1, lsl #15] @ encoding: [0x81,0x77,0x1c,0xe7]
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@ CHECK: ldr r5, [r2], r9, asr #15 @ encoding: [0xc9,0x57,0x92,0xe6]
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