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4658ba13a8
*or g0, x add g0, x recognized * as a move) or x, g0 add x, g0 or 0, x add 0, x or x, 0 add x, 0 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18793 91177308-0d34-0410-b5e6-96231b3b80d8
64 lines
2.3 KiB
C++
64 lines
2.3 KiB
C++
//===- SparcV8InstrInfo.cpp - SparcV8 Instruction Information ---*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the SparcV8 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "SparcV8InstrInfo.h"
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#include "SparcV8.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "SparcV8GenInstrInfo.inc"
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using namespace llvm;
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SparcV8InstrInfo::SparcV8InstrInfo()
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: TargetInstrInfo(SparcV8Insts, sizeof(SparcV8Insts)/sizeof(SparcV8Insts[0])){
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}
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static bool isZeroImmed (const MachineOperand &op) {
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return (op.isImmediate() && op.getImmedValue() == 0);
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}
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/// Return true if the instruction is a register to register move and
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/// leave the source and dest operands in the passed parameters.
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///
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bool SparcV8InstrInfo::isMoveInstr(const MachineInstr &MI,
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unsigned &SrcReg, unsigned &DstReg) const {
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// We look for 3 kinds of patterns here:
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// or with G0 or 0
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// add with G0 or 0
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// fmovs or FpMOVD (pseudo double move).
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if (MI.getOpcode() == V8::ORrr || MI.getOpcode() == V8::ADDrr) {
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if (MI.getOperand(1).getReg() == V8::G0) {
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DstReg = MI.getOperand(0).getReg();
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SrcReg = MI.getOperand(2).getReg();
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return true;
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} else if (MI.getOperand (2).getReg() == V8::G0) {
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DstReg = MI.getOperand(0).getReg();
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SrcReg = MI.getOperand(1).getReg();
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return true;
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}
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} else if (MI.getOpcode() == V8::ORri || MI.getOpcode() == V8::ADDri) {
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if (isZeroImmed (MI.getOperand (1))) {
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DstReg = MI.getOperand(0).getReg();
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SrcReg = MI.getOperand(2).getReg();
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return true;
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} else if (isZeroImmed (MI.getOperand (2))) {
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DstReg = MI.getOperand(0).getReg();
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SrcReg = MI.getOperand(1).getReg();
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return true;
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}
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} else if (MI.getOpcode() == V8::FMOVS || MI.getOpcode() == V8::FpMOVD) {
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SrcReg = MI.getOperand(1).getReg();
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DstReg = MI.getOperand(0).getReg();
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return true;
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}
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return false;
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}
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