mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-11-03 14:21:30 +00:00
8dac19c070
The backend previously folded offsets into PC-relative addresses whereever possible. That's the right thing to do when the address can be used directly in a PC-relative memory reference (using things like LRL). But if we have a register-based memory reference and need to load the PC-relative address separately, it's better to use an anchor point that could be shared with other accesses to the same area of the variable. Fixes a FIXME. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191524 91177308-0d34-0410-b5e6-96231b3b80d8
135 lines
3.3 KiB
LLVM
135 lines
3.3 KiB
LLVM
; Test 32-bit GPR accesses to a PC-relative location.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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@gsrc16 = global i16 1
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@gsrc32 = global i32 1
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@gdst16 = global i16 2
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@gdst32 = global i32 2
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@gsrc16u = global i16 1, align 1, section "foo"
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@gsrc32u = global i32 1, align 2, section "foo"
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@gdst16u = global i16 2, align 1, section "foo"
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@gdst32u = global i32 2, align 2, section "foo"
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@garray8 = global [2 x i8] [i8 100, i8 101]
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@garray16 = global [2 x i16] [i16 102, i16 103]
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; Check sign-extending loads from i16.
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define i32 @f1() {
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; CHECK-LABEL: f1:
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; CHECK: lhrl %r2, gsrc16
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; CHECK: br %r14
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%val = load i16 *@gsrc16
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%ext = sext i16 %val to i32
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ret i32 %ext
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}
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; Check zero-extending loads from i16.
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define i32 @f2() {
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; CHECK-LABEL: f2:
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; CHECK: llhrl %r2, gsrc16
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; CHECK: br %r14
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%val = load i16 *@gsrc16
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%ext = zext i16 %val to i32
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ret i32 %ext
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}
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; Check truncating 16-bit stores.
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define void @f3(i32 %val) {
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; CHECK-LABEL: f3:
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; CHECK: sthrl %r2, gdst16
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; CHECK: br %r14
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%half = trunc i32 %val to i16
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store i16 %half, i16 *@gdst16
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ret void
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}
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; Check plain loads and stores.
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define void @f4() {
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; CHECK-LABEL: f4:
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; CHECK: lrl %r0, gsrc32
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; CHECK: strl %r0, gdst32
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; CHECK: br %r14
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%val = load i32 *@gsrc32
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store i32 %val, i32 *@gdst32
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ret void
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}
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; Repeat f1 with an unaligned variable.
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define i32 @f5() {
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; CHECK-LABEL: f5:
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; CHECK: lgrl [[REG:%r[0-5]]], gsrc16u
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; CHECK: lh %r2, 0([[REG]])
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; CHECK: br %r14
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%val = load i16 *@gsrc16u, align 1
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%ext = sext i16 %val to i32
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ret i32 %ext
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}
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; Repeat f2 with an unaligned variable.
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define i32 @f6() {
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; CHECK-LABEL: f6:
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; CHECK: lgrl [[REG:%r[0-5]]], gsrc16u
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; CHECK: llh %r2, 0([[REG]])
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; CHECK: br %r14
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%val = load i16 *@gsrc16u, align 1
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%ext = zext i16 %val to i32
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ret i32 %ext
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}
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; Repeat f3 with an unaligned variable.
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define void @f7(i32 %val) {
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; CHECK-LABEL: f7:
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; CHECK: lgrl [[REG:%r[0-5]]], gdst16u
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; CHECK: sth %r2, 0([[REG]])
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; CHECK: br %r14
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%half = trunc i32 %val to i16
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store i16 %half, i16 *@gdst16u, align 1
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ret void
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}
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; Repeat f4 with unaligned variables.
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define void @f8() {
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; CHECK-LABEL: f8:
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; CHECK: larl [[REG:%r[0-5]]], gsrc32u
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; CHECK: l [[VAL:%r[0-5]]], 0([[REG]])
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; CHECK: larl [[REG:%r[0-5]]], gdst32u
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; CHECK: st [[VAL]], 0([[REG]])
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; CHECK: br %r14
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%val = load i32 *@gsrc32u, align 2
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store i32 %val, i32 *@gdst32u, align 2
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ret void
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}
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; Test a case where we want to use one LARL for accesses to two different
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; parts of a variable.
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define void @f9() {
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; CHECK-LABEL: f9:
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; CHECK: larl [[REG:%r[0-5]]], garray8
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; CHECK: llc [[VAL:%r[0-5]]], 0([[REG]])
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; CHECK: srl [[VAL]], 1
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; CHECK: stc [[VAL]], 1([[REG]])
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; CHECK: br %r14
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%ptr1 = getelementptr [2 x i8] *@garray8, i64 0, i64 0
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%ptr2 = getelementptr [2 x i8] *@garray8, i64 0, i64 1
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%val = load i8 *%ptr1
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%shr = lshr i8 %val, 1
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store i8 %shr, i8 *%ptr2
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ret void
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}
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; Test a case where we want to use separate relative-long addresses for
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; two different parts of a variable.
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define void @f10() {
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; CHECK-LABEL: f10:
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; CHECK: llhrl [[VAL:%r[0-5]]], garray16
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; CHECK: srl [[VAL]], 1
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; CHECK: sthrl [[VAL]], garray16+2
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; CHECK: br %r14
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%ptr1 = getelementptr [2 x i16] *@garray16, i64 0, i64 0
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%ptr2 = getelementptr [2 x i16] *@garray16, i64 0, i64 1
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%val = load i16 *%ptr1
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%shr = lshr i16 %val, 1
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store i16 %shr, i16 *%ptr2
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ret void
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}
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