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https://github.com/c64scene-ar/llvm-6502.git
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acb31a245c
At the moment we expect rotates to have the form: (or (shl X, Y), (shr X, Z)) where Y == bitsize(X) - Z or Z == bitsize(X) - Y. This form means that the (or ...) is undefined for Y == 0 or Z == 0. This undefinedness can be avoided by using Y == (C * bitsize(X) - Z) & (bitsize(X) - 1) or Z == (C * bitsize(X) - Y) & (bitsize(X) - 1) for any integer C (including 0, the most natural choice). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198861 91177308-0d34-0410-b5e6-96231b3b80d8
291 lines
6.7 KiB
LLVM
291 lines
6.7 KiB
LLVM
; Test 32-bit rotates left.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; Check the low end of the RLL range.
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define i32 @f1(i32 %a) {
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; CHECK-LABEL: f1:
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; CHECK: rll %r2, %r2, 1
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; CHECK: br %r14
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%parta = shl i32 %a, 1
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%partb = lshr i32 %a, 31
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%or = or i32 %parta, %partb
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ret i32 %or
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}
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; Check the high end of the defined RLL range.
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define i32 @f2(i32 %a) {
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; CHECK-LABEL: f2:
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; CHECK: rll %r2, %r2, 31
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; CHECK: br %r14
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%parta = shl i32 %a, 31
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%partb = lshr i32 %a, 1
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%or = or i32 %parta, %partb
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ret i32 %or
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}
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; We don't generate shifts by out-of-range values.
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define i32 @f3(i32 %a) {
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; CHECK-LABEL: f3:
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; CHECK-NOT: rll
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; CHECK: br %r14
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%parta = shl i32 %a, 32
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%partb = lshr i32 %a, 0
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%or = or i32 %parta, %partb
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ret i32 %or
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}
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; Check variable shifts.
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define i32 @f4(i32 %a, i32 %amt) {
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; CHECK-LABEL: f4:
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; CHECK: rll %r2, %r2, 0(%r3)
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; CHECK: br %r14
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%amtb = sub i32 32, %amt
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%parta = shl i32 %a, %amt
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%partb = lshr i32 %a, %amtb
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%or = or i32 %parta, %partb
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ret i32 %or
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}
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; Check shift amounts that have a constant term.
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define i32 @f5(i32 %a, i32 %amt) {
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; CHECK-LABEL: f5:
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; CHECK: rll %r2, %r2, 10(%r3)
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; CHECK: br %r14
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%add = add i32 %amt, 10
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%sub = sub i32 32, %add
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%parta = shl i32 %a, %add
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%partb = lshr i32 %a, %sub
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%or = or i32 %parta, %partb
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ret i32 %or
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}
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; ...and again with a truncated 64-bit shift amount.
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define i32 @f6(i32 %a, i64 %amt) {
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; CHECK-LABEL: f6:
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; CHECK: rll %r2, %r2, 10(%r3)
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; CHECK: br %r14
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%add = add i64 %amt, 10
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%addtrunc = trunc i64 %add to i32
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%sub = sub i32 32, %addtrunc
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%parta = shl i32 %a, %addtrunc
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%partb = lshr i32 %a, %sub
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%or = or i32 %parta, %partb
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ret i32 %or
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}
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; ...and again with a different truncation representation.
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define i32 @f7(i32 %a, i64 %amt) {
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; CHECK-LABEL: f7:
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; CHECK: rll %r2, %r2, 10(%r3)
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; CHECK: br %r14
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%add = add i64 %amt, 10
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%sub = sub i64 32, %add
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%addtrunc = trunc i64 %add to i32
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%subtrunc = trunc i64 %sub to i32
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%parta = shl i32 %a, %addtrunc
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%partb = lshr i32 %a, %subtrunc
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%or = or i32 %parta, %partb
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ret i32 %or
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}
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; Check shift amounts that have the largest in-range constant term. We could
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; mask the amount instead.
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define i32 @f8(i32 %a, i32 %amt) {
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; CHECK-LABEL: f8:
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; CHECK: rll %r2, %r2, 524287(%r3)
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; CHECK: br %r14
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%add = add i32 %amt, 524287
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%sub = sub i32 32, %add
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%parta = shl i32 %a, %add
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%partb = lshr i32 %a, %sub
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%or = or i32 %parta, %partb
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ret i32 %or
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}
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; Check the next value up, which without masking must use a separate
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; addition.
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define i32 @f9(i32 %a, i32 %amt) {
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; CHECK-LABEL: f9:
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; CHECK: afi %r3, 524288
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; CHECK: rll %r2, %r2, 0(%r3)
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; CHECK: br %r14
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%add = add i32 %amt, 524288
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%sub = sub i32 32, %add
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%parta = shl i32 %a, %add
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%partb = lshr i32 %a, %sub
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%or = or i32 %parta, %partb
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ret i32 %or
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}
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; Check cases where 1 is subtracted from the shift amount.
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define i32 @f10(i32 %a, i32 %amt) {
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; CHECK-LABEL: f10:
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; CHECK: rll %r2, %r2, -1(%r3)
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; CHECK: br %r14
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%suba = sub i32 %amt, 1
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%subb = sub i32 32, %suba
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%parta = shl i32 %a, %suba
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%partb = lshr i32 %a, %subb
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%or = or i32 %parta, %partb
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ret i32 %or
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}
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; Check the lowest value that can be subtracted from the shift amount.
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; Again, we could mask the shift amount instead.
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define i32 @f11(i32 %a, i32 %amt) {
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; CHECK-LABEL: f11:
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; CHECK: rll %r2, %r2, -524288(%r3)
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; CHECK: br %r14
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%suba = sub i32 %amt, 524288
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%subb = sub i32 32, %suba
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%parta = shl i32 %a, %suba
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%partb = lshr i32 %a, %subb
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%or = or i32 %parta, %partb
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ret i32 %or
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}
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; Check the next value down, which without masking must use a separate
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; addition.
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define i32 @f12(i32 %a, i32 %amt) {
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; CHECK-LABEL: f12:
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; CHECK: afi %r3, -524289
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; CHECK: rll %r2, %r2, 0(%r3)
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; CHECK: br %r14
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%suba = sub i32 %amt, 524289
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%subb = sub i32 32, %suba
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%parta = shl i32 %a, %suba
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%partb = lshr i32 %a, %subb
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%or = or i32 %parta, %partb
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ret i32 %or
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}
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; Check that we don't try to generate "indexed" shifts.
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define i32 @f13(i32 %a, i32 %b, i32 %c) {
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; CHECK-LABEL: f13:
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; CHECK: ar {{%r3, %r4|%r4, %r3}}
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; CHECK: rll %r2, %r2, 0({{%r[34]}})
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; CHECK: br %r14
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%add = add i32 %b, %c
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%sub = sub i32 32, %add
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%parta = shl i32 %a, %add
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%partb = lshr i32 %a, %sub
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%or = or i32 %parta, %partb
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ret i32 %or
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}
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; Check that the shift amount uses an address register. It cannot be in %r0.
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define i32 @f14(i32 %a, i32 *%ptr) {
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; CHECK-LABEL: f14:
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; CHECK: l %r1, 0(%r3)
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; CHECK: rll %r2, %r2, 0(%r1)
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; CHECK: br %r14
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%amt = load i32 *%ptr
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%amtb = sub i32 32, %amt
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%parta = shl i32 %a, %amt
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%partb = lshr i32 %a, %amtb
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%or = or i32 %parta, %partb
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ret i32 %or
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}
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; Check another form of f5, which is the one produced by running f5 through
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; instcombine.
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define i32 @f15(i32 %a, i32 %amt) {
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; CHECK-LABEL: f15:
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; CHECK: rll %r2, %r2, 10(%r3)
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; CHECK: br %r14
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%add = add i32 %amt, 10
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%sub = sub i32 22, %amt
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%parta = shl i32 %a, %add
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%partb = lshr i32 %a, %sub
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%or = or i32 %parta, %partb
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ret i32 %or
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}
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; Likewise for f7.
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define i32 @f16(i32 %a, i64 %amt) {
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; CHECK-LABEL: f16:
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; CHECK: rll %r2, %r2, 10(%r3)
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; CHECK: br %r14
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%add = add i64 %amt, 10
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%sub = sub i64 22, %amt
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%addtrunc = trunc i64 %add to i32
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%subtrunc = trunc i64 %sub to i32
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%parta = shl i32 %a, %addtrunc
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%partb = lshr i32 %a, %subtrunc
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%or = or i32 %parta, %partb
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ret i32 %or
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}
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; Check cases where (-x & 31) is used instead of 32 - x.
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define i32 @f17(i32 %x, i32 %y) {
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; CHECK-LABEL: f17:
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; CHECK: rll %r2, %r2, 0(%r3)
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; CHECK: br %r14
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entry:
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%shl = shl i32 %x, %y
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%sub = sub i32 0, %y
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%and = and i32 %sub, 31
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%shr = lshr i32 %x, %and
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%or = or i32 %shr, %shl
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ret i32 %or
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}
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; ...and again with ((32 - x) & 31).
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define i32 @f18(i32 %x, i32 %y) {
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; CHECK-LABEL: f18:
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; CHECK: rll %r2, %r2, 0(%r3)
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; CHECK: br %r14
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entry:
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%shl = shl i32 %x, %y
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%sub = sub i32 32, %y
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%and = and i32 %sub, 31
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%shr = lshr i32 %x, %and
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%or = or i32 %shr, %shl
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ret i32 %or
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}
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; This is not a rotation.
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define i32 @f19(i32 %x, i32 %y) {
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; CHECK-LABEL: f19:
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; CHECK-NOT: rll
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; CHECK: br %r14
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entry:
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%shl = shl i32 %x, %y
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%sub = sub i32 16, %y
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%and = and i32 %sub, 31
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%shr = lshr i32 %x, %and
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%or = or i32 %shr, %shl
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ret i32 %or
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}
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; Repeat f17 with an addition on the shift count.
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define i32 @f20(i32 %x, i32 %y) {
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; CHECK-LABEL: f20:
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; CHECK: rll %r2, %r2, 199(%r3)
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; CHECK: br %r14
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entry:
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%add = add i32 %y, 199
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%shl = shl i32 %x, %add
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%sub = sub i32 0, %add
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%and = and i32 %sub, 31
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%shr = lshr i32 %x, %and
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%or = or i32 %shr, %shl
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ret i32 %or
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}
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; ...and again with the InstCombine version.
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define i32 @f21(i32 %x, i32 %y) {
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; CHECK-LABEL: f21:
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; CHECK: rll %r2, %r2, 199(%r3)
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; CHECK: br %r14
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entry:
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%add = add i32 %y, 199
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%shl = shl i32 %x, %add
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%sub = sub i32 -199, %y
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%and = and i32 %sub, 31
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%shr = lshr i32 %x, %and
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%or = or i32 %shr, %shl
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ret i32 %or
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}
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