Bill Wendling bdf9db6f49 Don't reserve the R0 and R1 registers here. We don't use these registers, and ...

marking them as "live-in" into a BB ruins some invariants that the back-end
tries to maintain.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150437 91177308-0d34-0410-b5e6-96231b3b80d8

2012-02-13 23:47:16 +00:00

..

CMakeLists.txt

fix cmake

2012-02-01 22:28:29 +00:00

DAGCombiner.cpp

Fix a bug in DAGCombine for the optimization of BUILD_VECTOR. We cant generate a shuffle node from two vectors of different types.

2012-02-13 12:42:26 +00:00

FastISel.cpp

[fast-isel] HandlePHINodesInSuccessorBlocks() can promite i8 and i16 types too.

2012-02-04 00:39:19 +00:00

FunctionLoweringInfo.cpp

Remove the eh.exception and eh.selector intrinsics. Also remove a hack to copy

2012-01-31 01:46:13 +00:00

InstrEmitter.cpp

Handle all live physreg defs in the same place.

2012-02-03 20:43:35 +00:00

InstrEmitter.h

…

LegalizeDAG.cpp

Convert assert(0) to llvm_unreachable

2012-02-05 08:31:47 +00:00

LegalizeFloatTypes.cpp

Convert assert(0) to llvm_unreachable

2012-02-05 08:31:47 +00:00

LegalizeIntegerTypes.cpp

Convert assert(0) to llvm_unreachable

2012-02-05 08:31:47 +00:00

LegalizeTypes.cpp

Remove unnecessary default cases in switches that cover all enum values.

2012-01-10 16:47:17 +00:00

LegalizeTypes.h

…

LegalizeTypesGeneric.cpp

Remove unnecessary default cases in switches that cover all enum values.

2012-01-10 16:47:17 +00:00

LegalizeVectorOps.cpp

Convert assert(0) to llvm_unreachable

2012-02-05 08:31:47 +00:00

LegalizeVectorTypes.cpp

On AVX, we can load v8i32 at a time. The bug happens when two uneven loads are used.

2012-01-11 20:19:17 +00:00

LLVMBuild.txt

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Makefile

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ResourcePriorityQueue.cpp

VLIW specific scheduler framework that utilizes deterministic finite automaton (DFA).

2012-02-01 22:13:57 +00:00

ScheduleDAGFast.cpp

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ScheduleDAGRRList.cpp

Add register mask support to ScheduleDAGRRList.

2012-02-13 23:25:24 +00:00

ScheduleDAGSDNodes.cpp

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ScheduleDAGSDNodes.h

Add a RegisterMaskSDNode class.

2012-01-18 23:52:12 +00:00

ScheduleDAGVLIW.cpp

VLIW specific scheduler framework that utilizes deterministic finite automaton (DFA).

2012-02-01 22:13:57 +00:00

SDNodeDbgValue.h

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SDNodeOrdering.h

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SelectionDAG.cpp

Put instruction names into an indexed string table on the side, removing a pointer from MCInstrDesc.

2012-02-10 13:18:44 +00:00

SelectionDAGBuilder.cpp

Don't reserve the R0 and R1 registers here. We don't use these registers, and

2012-02-13 23:47:16 +00:00

SelectionDAGBuilder.h

[unwind removal] Remove all of the code for the dead 'unwind' instruction. There

2012-02-06 21:44:22 +00:00

SelectionDAGISel.cpp

[unwind removal] Remove all of the code for the dead 'unwind' instruction. There

2012-02-06 21:44:22 +00:00

SelectionDAGPrinter.cpp

drop unneeded config.h includes

2011-12-22 23:04:07 +00:00

TargetLowering.cpp

Use the correct ShiftAmtTy for creating shifts after legalization. PR11881. Not committing a testcase because I think it will be too fragile.

2012-01-31 01:08:03 +00:00

TargetSelectionDAGInfo.cpp

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