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75bb472c06
Summary: [asan-asm-instrumentation] Added comment describing how asm instrumentation works. Reviewers: eugenis Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5970 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220670 91177308-0d34-0410-b5e6-96231b3b80d8
1065 lines
39 KiB
C++
1065 lines
39 KiB
C++
//===-- X86AsmInstrumentation.cpp - Instrument X86 inline assembly C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/X86BaseInfo.h"
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#include "X86AsmInstrumentation.h"
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#include "X86Operand.h"
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#include "X86RegisterInfo.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/CodeGen/MachineValueType.h"
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#include "llvm/IR/Function.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstBuilder.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MCTargetAsmParser.h"
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#include "llvm/MC/MCTargetOptions.h"
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#include "llvm/Support/CommandLine.h"
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#include <algorithm>
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#include <cassert>
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#include <vector>
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// Following comment describes how assembly instrumentation works.
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// Currently we have only AddressSanitizer instrumentation, but we're
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// planning to implement MemorySanitizer for inline assembly too. If
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// you're not familiar with AddressSanitizer algorithm, please, read
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// https://code.google.com/p/address-sanitizer/wiki/AddressSanitizerAlgorithm.
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//
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// When inline assembly is parsed by an instance of X86AsmParser, all
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// instructions are emitted via EmitInstruction method. That's the
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// place where X86AsmInstrumentation analyzes an instruction and
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// decides, whether the instruction should be emitted as is or
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// instrumentation is required. The latter case happens when an
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// instruction reads from or writes to memory. Now instruction opcode
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// is explicitly checked, and if an instruction has a memory operand
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// (for instance, movq (%rsi, %rcx, 8), %rax) - it should be
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// instrumented. There're also exist instructions that modify
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// memory but don't have an explicit memory operands, for instance,
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// movs.
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//
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// Let's consider at first 8-byte memory accesses when an instruction
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// has an explicit memory operand. In this case we need two registers -
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// AddressReg to compute address of a memory cells which are accessed
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// and ShadowReg to compute corresponding shadow address. So, we need
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// to spill both registers before instrumentation code and restore them
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// after instrumentation. Thus, in general, instrumentation code will
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// look like this:
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// PUSHF # Store flags, otherwise they will be overwritten
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// PUSH AddressReg # spill AddressReg
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// PUSH ShadowReg # spill ShadowReg
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// LEA MemOp, AddressReg # compute address of the memory operand
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// MOV AddressReg, ShadowReg
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// SHR ShadowReg, 3
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// # ShadowOffset(AddressReg >> 3) contains address of a shadow
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// # corresponding to MemOp.
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// CMP ShadowOffset(ShadowReg), 0 # test shadow value
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// JZ .Done # when shadow equals to zero, everything is fine
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// MOV AddressReg, RDI
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// # Call __asan_report function with AddressReg as an argument
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// CALL __asan_report
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// .Done:
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// POP ShadowReg # Restore ShadowReg
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// POP AddressReg # Restore AddressReg
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// POPF # Restore flags
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//
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// Memory accesses with different size (1-, 2-, 4- and 16-byte) are
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// handled in a similar manner, but small memory accesses (less than 8
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// byte) require an additional ScratchReg, which is used for shadow value.
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//
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// If, suppose, we're instrumenting an instruction like movs, only
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// contents of RDI, RDI + AccessSize * RCX, RSI, RSI + AccessSize *
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// RCX are checked. In this case there're no need to spill and restore
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// AddressReg , ShadowReg or flags four times, they're saved on stack
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// just once, before instrumentation of these four addresses, and restored
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// at the end of the instrumentation.
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//
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// There exist several things which complicate this simple algorithm.
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// * Instrumented memory operand can have RSP as a base or an index
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// register. So we need to add a constant offset before computation
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// of memory address, since flags, AddressReg, ShadowReg, etc. were
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// already stored on stack and RSP was modified.
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// * Debug info (usually, DWARF) should be adjusted, because sometimes
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// RSP is used as a frame register. So, we need to select some
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// register as a frame register and temprorary override current CFA
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// register.
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namespace llvm {
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namespace {
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static cl::opt<bool> ClAsanInstrumentAssembly(
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"asan-instrument-assembly",
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cl::desc("instrument assembly with AddressSanitizer checks"), cl::Hidden,
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cl::init(false));
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const int64_t MinAllowedDisplacement = std::numeric_limits<int32_t>::min();
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const int64_t MaxAllowedDisplacement = std::numeric_limits<int32_t>::max();
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int64_t ApplyDisplacementBounds(int64_t Displacement) {
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return std::max(std::min(MaxAllowedDisplacement, Displacement),
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MinAllowedDisplacement);
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}
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void CheckDisplacementBounds(int64_t Displacement) {
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assert(Displacement >= MinAllowedDisplacement &&
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Displacement <= MaxAllowedDisplacement);
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}
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bool IsStackReg(unsigned Reg) { return Reg == X86::RSP || Reg == X86::ESP; }
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bool IsSmallMemAccess(unsigned AccessSize) { return AccessSize < 8; }
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std::string FuncName(unsigned AccessSize, bool IsWrite) {
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return std::string("__asan_report_") + (IsWrite ? "store" : "load") +
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utostr(AccessSize);
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}
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class X86AddressSanitizer : public X86AsmInstrumentation {
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public:
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struct RegisterContext {
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private:
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enum RegOffset {
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REG_OFFSET_ADDRESS = 0,
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REG_OFFSET_SHADOW,
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REG_OFFSET_SCRATCH
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};
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public:
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RegisterContext(unsigned AddressReg, unsigned ShadowReg,
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unsigned ScratchReg) {
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BusyRegs.push_back(convReg(AddressReg, MVT::i64));
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BusyRegs.push_back(convReg(ShadowReg, MVT::i64));
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BusyRegs.push_back(convReg(ScratchReg, MVT::i64));
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}
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unsigned AddressReg(MVT::SimpleValueType VT) const {
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return convReg(BusyRegs[REG_OFFSET_ADDRESS], VT);
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}
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unsigned ShadowReg(MVT::SimpleValueType VT) const {
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return convReg(BusyRegs[REG_OFFSET_SHADOW], VT);
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}
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unsigned ScratchReg(MVT::SimpleValueType VT) const {
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return convReg(BusyRegs[REG_OFFSET_SCRATCH], VT);
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}
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void AddBusyReg(unsigned Reg) {
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if (Reg != X86::NoRegister)
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BusyRegs.push_back(convReg(Reg, MVT::i64));
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}
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void AddBusyRegs(const X86Operand &Op) {
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AddBusyReg(Op.getMemBaseReg());
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AddBusyReg(Op.getMemIndexReg());
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}
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unsigned ChooseFrameReg(MVT::SimpleValueType VT) const {
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static const unsigned Candidates[] = { X86::RBP, X86::RAX, X86::RBX,
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X86::RCX, X86::RDX, X86::RDI,
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X86::RSI };
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for (unsigned Reg : Candidates) {
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if (!std::count(BusyRegs.begin(), BusyRegs.end(), Reg))
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return convReg(Reg, VT);
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}
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return X86::NoRegister;
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}
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private:
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unsigned convReg(unsigned Reg, MVT::SimpleValueType VT) const {
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return Reg == X86::NoRegister ? Reg : getX86SubSuperRegister(Reg, VT);
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}
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std::vector<unsigned> BusyRegs;
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};
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X86AddressSanitizer(const MCSubtargetInfo &STI)
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: X86AsmInstrumentation(STI), RepPrefix(false), OrigSPOffset(0) {}
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virtual ~X86AddressSanitizer() {}
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// X86AsmInstrumentation implementation:
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virtual void InstrumentAndEmitInstruction(const MCInst &Inst,
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OperandVector &Operands,
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MCContext &Ctx,
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const MCInstrInfo &MII,
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MCStreamer &Out) override {
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InstrumentMOVS(Inst, Operands, Ctx, MII, Out);
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if (RepPrefix)
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EmitInstruction(Out, MCInstBuilder(X86::REP_PREFIX));
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InstrumentMOV(Inst, Operands, Ctx, MII, Out);
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RepPrefix = (Inst.getOpcode() == X86::REP_PREFIX);
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if (!RepPrefix)
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EmitInstruction(Out, Inst);
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}
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// Adjusts up stack and saves all registers used in instrumentation.
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virtual void InstrumentMemOperandPrologue(const RegisterContext &RegCtx,
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MCContext &Ctx,
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MCStreamer &Out) = 0;
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// Restores all registers used in instrumentation and adjusts stack.
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virtual void InstrumentMemOperandEpilogue(const RegisterContext &RegCtx,
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MCContext &Ctx,
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MCStreamer &Out) = 0;
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virtual void InstrumentMemOperandSmall(X86Operand &Op, unsigned AccessSize,
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bool IsWrite,
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const RegisterContext &RegCtx,
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MCContext &Ctx, MCStreamer &Out) = 0;
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virtual void InstrumentMemOperandLarge(X86Operand &Op, unsigned AccessSize,
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bool IsWrite,
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const RegisterContext &RegCtx,
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MCContext &Ctx, MCStreamer &Out) = 0;
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virtual void InstrumentMOVSImpl(unsigned AccessSize, MCContext &Ctx,
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MCStreamer &Out) = 0;
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void InstrumentMemOperand(X86Operand &Op, unsigned AccessSize, bool IsWrite,
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const RegisterContext &RegCtx, MCContext &Ctx,
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MCStreamer &Out);
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void InstrumentMOVSBase(unsigned DstReg, unsigned SrcReg, unsigned CntReg,
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unsigned AccessSize, MCContext &Ctx, MCStreamer &Out);
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void InstrumentMOVS(const MCInst &Inst, OperandVector &Operands,
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MCContext &Ctx, const MCInstrInfo &MII, MCStreamer &Out);
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void InstrumentMOV(const MCInst &Inst, OperandVector &Operands,
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MCContext &Ctx, const MCInstrInfo &MII, MCStreamer &Out);
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protected:
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void EmitLabel(MCStreamer &Out, MCSymbol *Label) { Out.EmitLabel(Label); }
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void EmitLEA(X86Operand &Op, MVT::SimpleValueType VT, unsigned Reg,
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MCStreamer &Out) {
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assert(VT == MVT::i32 || VT == MVT::i64);
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MCInst Inst;
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Inst.setOpcode(VT == MVT::i32 ? X86::LEA32r : X86::LEA64r);
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Inst.addOperand(MCOperand::CreateReg(getX86SubSuperRegister(Reg, VT)));
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Op.addMemOperands(Inst, 5);
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EmitInstruction(Out, Inst);
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}
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void ComputeMemOperandAddress(X86Operand &Op, MVT::SimpleValueType VT,
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unsigned Reg, MCContext &Ctx, MCStreamer &Out);
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// Creates new memory operand with Displacement added to an original
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// displacement. Residue will contain a residue which could happen when the
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// total displacement exceeds 32-bit limitation.
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std::unique_ptr<X86Operand> AddDisplacement(X86Operand &Op,
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int64_t Displacement,
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MCContext &Ctx, int64_t *Residue);
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// True when previous instruction was actually REP prefix.
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bool RepPrefix;
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// Offset from the original SP register.
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int64_t OrigSPOffset;
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};
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void X86AddressSanitizer::InstrumentMemOperand(
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X86Operand &Op, unsigned AccessSize, bool IsWrite,
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const RegisterContext &RegCtx, MCContext &Ctx, MCStreamer &Out) {
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assert(Op.isMem() && "Op should be a memory operand.");
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assert((AccessSize & (AccessSize - 1)) == 0 && AccessSize <= 16 &&
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"AccessSize should be a power of two, less or equal than 16.");
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// FIXME: take into account load/store alignment.
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if (IsSmallMemAccess(AccessSize))
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InstrumentMemOperandSmall(Op, AccessSize, IsWrite, RegCtx, Ctx, Out);
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else
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InstrumentMemOperandLarge(Op, AccessSize, IsWrite, RegCtx, Ctx, Out);
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}
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void X86AddressSanitizer::InstrumentMOVSBase(unsigned DstReg, unsigned SrcReg,
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unsigned CntReg,
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unsigned AccessSize,
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MCContext &Ctx, MCStreamer &Out) {
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// FIXME: check whole ranges [DstReg .. DstReg + AccessSize * (CntReg - 1)]
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// and [SrcReg .. SrcReg + AccessSize * (CntReg - 1)].
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RegisterContext RegCtx(X86::RDX /* AddressReg */, X86::RAX /* ShadowReg */,
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IsSmallMemAccess(AccessSize)
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? X86::RBX
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: X86::NoRegister /* ScratchReg */);
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RegCtx.AddBusyReg(DstReg);
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RegCtx.AddBusyReg(SrcReg);
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RegCtx.AddBusyReg(CntReg);
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InstrumentMemOperandPrologue(RegCtx, Ctx, Out);
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// Test (%SrcReg)
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{
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const MCExpr *Disp = MCConstantExpr::Create(0, Ctx);
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std::unique_ptr<X86Operand> Op(X86Operand::CreateMem(
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0, Disp, SrcReg, 0, AccessSize, SMLoc(), SMLoc()));
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InstrumentMemOperand(*Op, AccessSize, false /* IsWrite */, RegCtx, Ctx,
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Out);
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}
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// Test -1(%SrcReg, %CntReg, AccessSize)
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{
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const MCExpr *Disp = MCConstantExpr::Create(-1, Ctx);
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std::unique_ptr<X86Operand> Op(X86Operand::CreateMem(
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0, Disp, SrcReg, CntReg, AccessSize, SMLoc(), SMLoc()));
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InstrumentMemOperand(*Op, AccessSize, false /* IsWrite */, RegCtx, Ctx,
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Out);
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}
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// Test (%DstReg)
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{
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const MCExpr *Disp = MCConstantExpr::Create(0, Ctx);
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std::unique_ptr<X86Operand> Op(X86Operand::CreateMem(
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0, Disp, DstReg, 0, AccessSize, SMLoc(), SMLoc()));
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InstrumentMemOperand(*Op, AccessSize, true /* IsWrite */, RegCtx, Ctx, Out);
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}
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// Test -1(%DstReg, %CntReg, AccessSize)
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{
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const MCExpr *Disp = MCConstantExpr::Create(-1, Ctx);
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std::unique_ptr<X86Operand> Op(X86Operand::CreateMem(
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0, Disp, DstReg, CntReg, AccessSize, SMLoc(), SMLoc()));
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InstrumentMemOperand(*Op, AccessSize, true /* IsWrite */, RegCtx, Ctx, Out);
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}
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InstrumentMemOperandEpilogue(RegCtx, Ctx, Out);
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}
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void X86AddressSanitizer::InstrumentMOVS(const MCInst &Inst,
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OperandVector &Operands,
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MCContext &Ctx, const MCInstrInfo &MII,
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MCStreamer &Out) {
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// Access size in bytes.
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unsigned AccessSize = 0;
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switch (Inst.getOpcode()) {
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case X86::MOVSB:
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AccessSize = 1;
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break;
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case X86::MOVSW:
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AccessSize = 2;
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break;
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case X86::MOVSL:
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AccessSize = 4;
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break;
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case X86::MOVSQ:
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AccessSize = 8;
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break;
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default:
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return;
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}
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InstrumentMOVSImpl(AccessSize, Ctx, Out);
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}
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void X86AddressSanitizer::InstrumentMOV(const MCInst &Inst,
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OperandVector &Operands, MCContext &Ctx,
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const MCInstrInfo &MII,
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MCStreamer &Out) {
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// Access size in bytes.
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unsigned AccessSize = 0;
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switch (Inst.getOpcode()) {
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case X86::MOV8mi:
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case X86::MOV8mr:
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case X86::MOV8rm:
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AccessSize = 1;
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break;
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case X86::MOV16mi:
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case X86::MOV16mr:
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case X86::MOV16rm:
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AccessSize = 2;
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break;
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case X86::MOV32mi:
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case X86::MOV32mr:
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case X86::MOV32rm:
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AccessSize = 4;
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break;
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case X86::MOV64mi32:
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case X86::MOV64mr:
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case X86::MOV64rm:
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AccessSize = 8;
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break;
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case X86::MOVAPDmr:
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case X86::MOVAPSmr:
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case X86::MOVAPDrm:
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case X86::MOVAPSrm:
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AccessSize = 16;
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break;
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default:
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return;
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}
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const bool IsWrite = MII.get(Inst.getOpcode()).mayStore();
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for (unsigned Ix = 0; Ix < Operands.size(); ++Ix) {
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assert(Operands[Ix]);
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MCParsedAsmOperand &Op = *Operands[Ix];
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if (Op.isMem()) {
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X86Operand &MemOp = static_cast<X86Operand &>(Op);
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RegisterContext RegCtx(
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X86::RDI /* AddressReg */, X86::RAX /* ShadowReg */,
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IsSmallMemAccess(AccessSize) ? X86::RCX
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: X86::NoRegister /* ScratchReg */);
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RegCtx.AddBusyRegs(MemOp);
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InstrumentMemOperandPrologue(RegCtx, Ctx, Out);
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InstrumentMemOperand(MemOp, AccessSize, IsWrite, RegCtx, Ctx, Out);
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InstrumentMemOperandEpilogue(RegCtx, Ctx, Out);
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}
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}
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}
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void X86AddressSanitizer::ComputeMemOperandAddress(X86Operand &Op,
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MVT::SimpleValueType VT,
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unsigned Reg, MCContext &Ctx,
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MCStreamer &Out) {
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int64_t Displacement = 0;
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if (IsStackReg(Op.getMemBaseReg()))
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Displacement -= OrigSPOffset;
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if (IsStackReg(Op.getMemIndexReg()))
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Displacement -= OrigSPOffset * Op.getMemScale();
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assert(Displacement >= 0);
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// Emit Op as is.
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if (Displacement == 0) {
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EmitLEA(Op, VT, Reg, Out);
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return;
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}
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int64_t Residue;
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std::unique_ptr<X86Operand> NewOp =
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AddDisplacement(Op, Displacement, Ctx, &Residue);
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EmitLEA(*NewOp, VT, Reg, Out);
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while (Residue != 0) {
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const MCConstantExpr *Disp =
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MCConstantExpr::Create(ApplyDisplacementBounds(Residue), Ctx);
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std::unique_ptr<X86Operand> DispOp =
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X86Operand::CreateMem(0, Disp, Reg, 0, 1, SMLoc(), SMLoc());
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EmitLEA(*DispOp, VT, Reg, Out);
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Residue -= Disp->getValue();
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}
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}
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std::unique_ptr<X86Operand>
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X86AddressSanitizer::AddDisplacement(X86Operand &Op, int64_t Displacement,
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MCContext &Ctx, int64_t *Residue) {
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|
assert(Displacement >= 0);
|
|
|
|
if (Displacement == 0 ||
|
|
(Op.getMemDisp() && Op.getMemDisp()->getKind() != MCExpr::Constant)) {
|
|
*Residue = Displacement;
|
|
return X86Operand::CreateMem(Op.getMemSegReg(), Op.getMemDisp(),
|
|
Op.getMemBaseReg(), Op.getMemIndexReg(),
|
|
Op.getMemScale(), SMLoc(), SMLoc());
|
|
}
|
|
|
|
int64_t OrigDisplacement =
|
|
static_cast<const MCConstantExpr *>(Op.getMemDisp())->getValue();
|
|
CheckDisplacementBounds(OrigDisplacement);
|
|
Displacement += OrigDisplacement;
|
|
|
|
int64_t NewDisplacement = ApplyDisplacementBounds(Displacement);
|
|
CheckDisplacementBounds(NewDisplacement);
|
|
|
|
*Residue = Displacement - NewDisplacement;
|
|
const MCExpr *Disp = MCConstantExpr::Create(NewDisplacement, Ctx);
|
|
return X86Operand::CreateMem(Op.getMemSegReg(), Disp, Op.getMemBaseReg(),
|
|
Op.getMemIndexReg(), Op.getMemScale(), SMLoc(),
|
|
SMLoc());
|
|
}
|
|
|
|
class X86AddressSanitizer32 : public X86AddressSanitizer {
|
|
public:
|
|
static const long kShadowOffset = 0x20000000;
|
|
|
|
X86AddressSanitizer32(const MCSubtargetInfo &STI)
|
|
: X86AddressSanitizer(STI) {}
|
|
|
|
virtual ~X86AddressSanitizer32() {}
|
|
|
|
unsigned GetFrameReg(const MCContext &Ctx, MCStreamer &Out) {
|
|
unsigned FrameReg = GetFrameRegGeneric(Ctx, Out);
|
|
if (FrameReg == X86::NoRegister)
|
|
return FrameReg;
|
|
return getX86SubSuperRegister(FrameReg, MVT::i32);
|
|
}
|
|
|
|
void SpillReg(MCStreamer &Out, unsigned Reg) {
|
|
EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(Reg));
|
|
OrigSPOffset -= 4;
|
|
}
|
|
|
|
void RestoreReg(MCStreamer &Out, unsigned Reg) {
|
|
EmitInstruction(Out, MCInstBuilder(X86::POP32r).addReg(Reg));
|
|
OrigSPOffset += 4;
|
|
}
|
|
|
|
void StoreFlags(MCStreamer &Out) {
|
|
EmitInstruction(Out, MCInstBuilder(X86::PUSHF32));
|
|
OrigSPOffset -= 4;
|
|
}
|
|
|
|
void RestoreFlags(MCStreamer &Out) {
|
|
EmitInstruction(Out, MCInstBuilder(X86::POPF32));
|
|
OrigSPOffset += 4;
|
|
}
|
|
|
|
virtual void InstrumentMemOperandPrologue(const RegisterContext &RegCtx,
|
|
MCContext &Ctx,
|
|
MCStreamer &Out) override {
|
|
unsigned LocalFrameReg = RegCtx.ChooseFrameReg(MVT::i32);
|
|
assert(LocalFrameReg != X86::NoRegister);
|
|
|
|
const MCRegisterInfo *MRI = Ctx.getRegisterInfo();
|
|
unsigned FrameReg = GetFrameReg(Ctx, Out);
|
|
if (MRI && FrameReg != X86::NoRegister) {
|
|
SpillReg(Out, LocalFrameReg);
|
|
if (FrameReg == X86::ESP) {
|
|
Out.EmitCFIAdjustCfaOffset(4 /* byte size of the LocalFrameReg */);
|
|
Out.EmitCFIRelOffset(
|
|
MRI->getDwarfRegNum(LocalFrameReg, true /* IsEH */), 0);
|
|
}
|
|
EmitInstruction(
|
|
Out,
|
|
MCInstBuilder(X86::MOV32rr).addReg(LocalFrameReg).addReg(FrameReg));
|
|
Out.EmitCFIRememberState();
|
|
Out.EmitCFIDefCfaRegister(
|
|
MRI->getDwarfRegNum(LocalFrameReg, true /* IsEH */));
|
|
}
|
|
|
|
SpillReg(Out, RegCtx.AddressReg(MVT::i32));
|
|
SpillReg(Out, RegCtx.ShadowReg(MVT::i32));
|
|
if (RegCtx.ScratchReg(MVT::i32) != X86::NoRegister)
|
|
SpillReg(Out, RegCtx.ScratchReg(MVT::i32));
|
|
StoreFlags(Out);
|
|
}
|
|
|
|
virtual void InstrumentMemOperandEpilogue(const RegisterContext &RegCtx,
|
|
MCContext &Ctx,
|
|
MCStreamer &Out) override {
|
|
unsigned LocalFrameReg = RegCtx.ChooseFrameReg(MVT::i32);
|
|
assert(LocalFrameReg != X86::NoRegister);
|
|
|
|
RestoreFlags(Out);
|
|
if (RegCtx.ScratchReg(MVT::i32) != X86::NoRegister)
|
|
RestoreReg(Out, RegCtx.ScratchReg(MVT::i32));
|
|
RestoreReg(Out, RegCtx.ShadowReg(MVT::i32));
|
|
RestoreReg(Out, RegCtx.AddressReg(MVT::i32));
|
|
|
|
unsigned FrameReg = GetFrameReg(Ctx, Out);
|
|
if (Ctx.getRegisterInfo() && FrameReg != X86::NoRegister) {
|
|
RestoreReg(Out, LocalFrameReg);
|
|
Out.EmitCFIRestoreState();
|
|
if (FrameReg == X86::ESP)
|
|
Out.EmitCFIAdjustCfaOffset(-4 /* byte size of the LocalFrameReg */);
|
|
}
|
|
}
|
|
|
|
virtual void InstrumentMemOperandSmall(X86Operand &Op, unsigned AccessSize,
|
|
bool IsWrite,
|
|
const RegisterContext &RegCtx,
|
|
MCContext &Ctx,
|
|
MCStreamer &Out) override;
|
|
virtual void InstrumentMemOperandLarge(X86Operand &Op, unsigned AccessSize,
|
|
bool IsWrite,
|
|
const RegisterContext &RegCtx,
|
|
MCContext &Ctx,
|
|
MCStreamer &Out) override;
|
|
virtual void InstrumentMOVSImpl(unsigned AccessSize, MCContext &Ctx,
|
|
MCStreamer &Out) override;
|
|
|
|
private:
|
|
void EmitCallAsanReport(unsigned AccessSize, bool IsWrite, MCContext &Ctx,
|
|
MCStreamer &Out, const RegisterContext &RegCtx) {
|
|
EmitInstruction(Out, MCInstBuilder(X86::CLD));
|
|
EmitInstruction(Out, MCInstBuilder(X86::MMX_EMMS));
|
|
|
|
EmitInstruction(Out, MCInstBuilder(X86::AND64ri8)
|
|
.addReg(X86::ESP)
|
|
.addReg(X86::ESP)
|
|
.addImm(-16));
|
|
EmitInstruction(
|
|
Out, MCInstBuilder(X86::PUSH32r).addReg(RegCtx.AddressReg(MVT::i32)));
|
|
|
|
const std::string &Fn = FuncName(AccessSize, IsWrite);
|
|
MCSymbol *FnSym = Ctx.GetOrCreateSymbol(StringRef(Fn));
|
|
const MCSymbolRefExpr *FnExpr =
|
|
MCSymbolRefExpr::Create(FnSym, MCSymbolRefExpr::VK_PLT, Ctx);
|
|
EmitInstruction(Out, MCInstBuilder(X86::CALLpcrel32).addExpr(FnExpr));
|
|
}
|
|
};
|
|
|
|
void X86AddressSanitizer32::InstrumentMemOperandSmall(
|
|
X86Operand &Op, unsigned AccessSize, bool IsWrite,
|
|
const RegisterContext &RegCtx, MCContext &Ctx, MCStreamer &Out) {
|
|
unsigned AddressRegI32 = RegCtx.AddressReg(MVT::i32);
|
|
unsigned ShadowRegI32 = RegCtx.ShadowReg(MVT::i32);
|
|
unsigned ShadowRegI8 = RegCtx.ShadowReg(MVT::i8);
|
|
|
|
assert(RegCtx.ScratchReg(MVT::i32) != X86::NoRegister);
|
|
unsigned ScratchRegI32 = RegCtx.ScratchReg(MVT::i32);
|
|
|
|
ComputeMemOperandAddress(Op, MVT::i32, AddressRegI32, Ctx, Out);
|
|
|
|
EmitInstruction(Out, MCInstBuilder(X86::MOV32rr).addReg(ShadowRegI32).addReg(
|
|
AddressRegI32));
|
|
EmitInstruction(Out, MCInstBuilder(X86::SHR32ri)
|
|
.addReg(ShadowRegI32)
|
|
.addReg(ShadowRegI32)
|
|
.addImm(3));
|
|
|
|
{
|
|
MCInst Inst;
|
|
Inst.setOpcode(X86::MOV8rm);
|
|
Inst.addOperand(MCOperand::CreateReg(ShadowRegI8));
|
|
const MCExpr *Disp = MCConstantExpr::Create(kShadowOffset, Ctx);
|
|
std::unique_ptr<X86Operand> Op(
|
|
X86Operand::CreateMem(0, Disp, ShadowRegI32, 0, 1, SMLoc(), SMLoc()));
|
|
Op->addMemOperands(Inst, 5);
|
|
EmitInstruction(Out, Inst);
|
|
}
|
|
|
|
EmitInstruction(
|
|
Out, MCInstBuilder(X86::TEST8rr).addReg(ShadowRegI8).addReg(ShadowRegI8));
|
|
MCSymbol *DoneSym = Ctx.CreateTempSymbol();
|
|
const MCExpr *DoneExpr = MCSymbolRefExpr::Create(DoneSym, Ctx);
|
|
EmitInstruction(Out, MCInstBuilder(X86::JE_4).addExpr(DoneExpr));
|
|
|
|
EmitInstruction(Out, MCInstBuilder(X86::MOV32rr).addReg(ScratchRegI32).addReg(
|
|
AddressRegI32));
|
|
EmitInstruction(Out, MCInstBuilder(X86::AND32ri)
|
|
.addReg(ScratchRegI32)
|
|
.addReg(ScratchRegI32)
|
|
.addImm(7));
|
|
|
|
switch (AccessSize) {
|
|
case 1:
|
|
break;
|
|
case 2: {
|
|
const MCExpr *Disp = MCConstantExpr::Create(1, Ctx);
|
|
std::unique_ptr<X86Operand> Op(
|
|
X86Operand::CreateMem(0, Disp, ScratchRegI32, 0, 1, SMLoc(), SMLoc()));
|
|
EmitLEA(*Op, MVT::i32, ScratchRegI32, Out);
|
|
break;
|
|
}
|
|
case 4:
|
|
EmitInstruction(Out, MCInstBuilder(X86::ADD32ri8)
|
|
.addReg(ScratchRegI32)
|
|
.addReg(ScratchRegI32)
|
|
.addImm(3));
|
|
break;
|
|
default:
|
|
assert(false && "Incorrect access size");
|
|
break;
|
|
}
|
|
|
|
EmitInstruction(
|
|
Out,
|
|
MCInstBuilder(X86::MOVSX32rr8).addReg(ShadowRegI32).addReg(ShadowRegI8));
|
|
EmitInstruction(Out, MCInstBuilder(X86::CMP32rr).addReg(ScratchRegI32).addReg(
|
|
ShadowRegI32));
|
|
EmitInstruction(Out, MCInstBuilder(X86::JL_4).addExpr(DoneExpr));
|
|
|
|
EmitCallAsanReport(AccessSize, IsWrite, Ctx, Out, RegCtx);
|
|
EmitLabel(Out, DoneSym);
|
|
}
|
|
|
|
void X86AddressSanitizer32::InstrumentMemOperandLarge(
|
|
X86Operand &Op, unsigned AccessSize, bool IsWrite,
|
|
const RegisterContext &RegCtx, MCContext &Ctx, MCStreamer &Out) {
|
|
unsigned AddressRegI32 = RegCtx.AddressReg(MVT::i32);
|
|
unsigned ShadowRegI32 = RegCtx.ShadowReg(MVT::i32);
|
|
|
|
ComputeMemOperandAddress(Op, MVT::i32, AddressRegI32, Ctx, Out);
|
|
|
|
EmitInstruction(Out, MCInstBuilder(X86::MOV32rr).addReg(ShadowRegI32).addReg(
|
|
AddressRegI32));
|
|
EmitInstruction(Out, MCInstBuilder(X86::SHR32ri)
|
|
.addReg(ShadowRegI32)
|
|
.addReg(ShadowRegI32)
|
|
.addImm(3));
|
|
{
|
|
MCInst Inst;
|
|
switch (AccessSize) {
|
|
case 8:
|
|
Inst.setOpcode(X86::CMP8mi);
|
|
break;
|
|
case 16:
|
|
Inst.setOpcode(X86::CMP16mi);
|
|
break;
|
|
default:
|
|
assert(false && "Incorrect access size");
|
|
break;
|
|
}
|
|
const MCExpr *Disp = MCConstantExpr::Create(kShadowOffset, Ctx);
|
|
std::unique_ptr<X86Operand> Op(
|
|
X86Operand::CreateMem(0, Disp, ShadowRegI32, 0, 1, SMLoc(), SMLoc()));
|
|
Op->addMemOperands(Inst, 5);
|
|
Inst.addOperand(MCOperand::CreateImm(0));
|
|
EmitInstruction(Out, Inst);
|
|
}
|
|
MCSymbol *DoneSym = Ctx.CreateTempSymbol();
|
|
const MCExpr *DoneExpr = MCSymbolRefExpr::Create(DoneSym, Ctx);
|
|
EmitInstruction(Out, MCInstBuilder(X86::JE_4).addExpr(DoneExpr));
|
|
|
|
EmitCallAsanReport(AccessSize, IsWrite, Ctx, Out, RegCtx);
|
|
EmitLabel(Out, DoneSym);
|
|
}
|
|
|
|
void X86AddressSanitizer32::InstrumentMOVSImpl(unsigned AccessSize,
|
|
MCContext &Ctx,
|
|
MCStreamer &Out) {
|
|
StoreFlags(Out);
|
|
|
|
// No need to test when ECX is equals to zero.
|
|
MCSymbol *DoneSym = Ctx.CreateTempSymbol();
|
|
const MCExpr *DoneExpr = MCSymbolRefExpr::Create(DoneSym, Ctx);
|
|
EmitInstruction(
|
|
Out, MCInstBuilder(X86::TEST32rr).addReg(X86::ECX).addReg(X86::ECX));
|
|
EmitInstruction(Out, MCInstBuilder(X86::JE_4).addExpr(DoneExpr));
|
|
|
|
// Instrument first and last elements in src and dst range.
|
|
InstrumentMOVSBase(X86::EDI /* DstReg */, X86::ESI /* SrcReg */,
|
|
X86::ECX /* CntReg */, AccessSize, Ctx, Out);
|
|
|
|
EmitLabel(Out, DoneSym);
|
|
RestoreFlags(Out);
|
|
}
|
|
|
|
class X86AddressSanitizer64 : public X86AddressSanitizer {
|
|
public:
|
|
static const long kShadowOffset = 0x7fff8000;
|
|
|
|
X86AddressSanitizer64(const MCSubtargetInfo &STI)
|
|
: X86AddressSanitizer(STI) {}
|
|
|
|
virtual ~X86AddressSanitizer64() {}
|
|
|
|
unsigned GetFrameReg(const MCContext &Ctx, MCStreamer &Out) {
|
|
unsigned FrameReg = GetFrameRegGeneric(Ctx, Out);
|
|
if (FrameReg == X86::NoRegister)
|
|
return FrameReg;
|
|
return getX86SubSuperRegister(FrameReg, MVT::i64);
|
|
}
|
|
|
|
void SpillReg(MCStreamer &Out, unsigned Reg) {
|
|
EmitInstruction(Out, MCInstBuilder(X86::PUSH64r).addReg(Reg));
|
|
OrigSPOffset -= 8;
|
|
}
|
|
|
|
void RestoreReg(MCStreamer &Out, unsigned Reg) {
|
|
EmitInstruction(Out, MCInstBuilder(X86::POP64r).addReg(Reg));
|
|
OrigSPOffset += 8;
|
|
}
|
|
|
|
void StoreFlags(MCStreamer &Out) {
|
|
EmitInstruction(Out, MCInstBuilder(X86::PUSHF64));
|
|
OrigSPOffset -= 8;
|
|
}
|
|
|
|
void RestoreFlags(MCStreamer &Out) {
|
|
EmitInstruction(Out, MCInstBuilder(X86::POPF64));
|
|
OrigSPOffset += 8;
|
|
}
|
|
|
|
virtual void InstrumentMemOperandPrologue(const RegisterContext &RegCtx,
|
|
MCContext &Ctx,
|
|
MCStreamer &Out) override {
|
|
unsigned LocalFrameReg = RegCtx.ChooseFrameReg(MVT::i64);
|
|
assert(LocalFrameReg != X86::NoRegister);
|
|
|
|
const MCRegisterInfo *MRI = Ctx.getRegisterInfo();
|
|
unsigned FrameReg = GetFrameReg(Ctx, Out);
|
|
if (MRI && FrameReg != X86::NoRegister) {
|
|
SpillReg(Out, X86::RBP);
|
|
if (FrameReg == X86::RSP) {
|
|
Out.EmitCFIAdjustCfaOffset(8 /* byte size of the LocalFrameReg */);
|
|
Out.EmitCFIRelOffset(
|
|
MRI->getDwarfRegNum(LocalFrameReg, true /* IsEH */), 0);
|
|
}
|
|
EmitInstruction(
|
|
Out,
|
|
MCInstBuilder(X86::MOV64rr).addReg(LocalFrameReg).addReg(FrameReg));
|
|
Out.EmitCFIRememberState();
|
|
Out.EmitCFIDefCfaRegister(
|
|
MRI->getDwarfRegNum(LocalFrameReg, true /* IsEH */));
|
|
}
|
|
|
|
EmitAdjustRSP(Ctx, Out, -128);
|
|
SpillReg(Out, RegCtx.ShadowReg(MVT::i64));
|
|
SpillReg(Out, RegCtx.AddressReg(MVT::i64));
|
|
if (RegCtx.ScratchReg(MVT::i64) != X86::NoRegister)
|
|
SpillReg(Out, RegCtx.ScratchReg(MVT::i64));
|
|
StoreFlags(Out);
|
|
}
|
|
|
|
virtual void InstrumentMemOperandEpilogue(const RegisterContext &RegCtx,
|
|
MCContext &Ctx,
|
|
MCStreamer &Out) override {
|
|
unsigned LocalFrameReg = RegCtx.ChooseFrameReg(MVT::i64);
|
|
assert(LocalFrameReg != X86::NoRegister);
|
|
|
|
RestoreFlags(Out);
|
|
if (RegCtx.ScratchReg(MVT::i64) != X86::NoRegister)
|
|
RestoreReg(Out, RegCtx.ScratchReg(MVT::i64));
|
|
RestoreReg(Out, RegCtx.AddressReg(MVT::i64));
|
|
RestoreReg(Out, RegCtx.ShadowReg(MVT::i64));
|
|
EmitAdjustRSP(Ctx, Out, 128);
|
|
|
|
unsigned FrameReg = GetFrameReg(Ctx, Out);
|
|
if (Ctx.getRegisterInfo() && FrameReg != X86::NoRegister) {
|
|
RestoreReg(Out, LocalFrameReg);
|
|
Out.EmitCFIRestoreState();
|
|
if (FrameReg == X86::RSP)
|
|
Out.EmitCFIAdjustCfaOffset(-8 /* byte size of the LocalFrameReg */);
|
|
}
|
|
}
|
|
|
|
virtual void InstrumentMemOperandSmall(X86Operand &Op, unsigned AccessSize,
|
|
bool IsWrite,
|
|
const RegisterContext &RegCtx,
|
|
MCContext &Ctx,
|
|
MCStreamer &Out) override;
|
|
virtual void InstrumentMemOperandLarge(X86Operand &Op, unsigned AccessSize,
|
|
bool IsWrite,
|
|
const RegisterContext &RegCtx,
|
|
MCContext &Ctx,
|
|
MCStreamer &Out) override;
|
|
virtual void InstrumentMOVSImpl(unsigned AccessSize, MCContext &Ctx,
|
|
MCStreamer &Out) override;
|
|
|
|
private:
|
|
void EmitAdjustRSP(MCContext &Ctx, MCStreamer &Out, long Offset) {
|
|
const MCExpr *Disp = MCConstantExpr::Create(Offset, Ctx);
|
|
std::unique_ptr<X86Operand> Op(
|
|
X86Operand::CreateMem(0, Disp, X86::RSP, 0, 1, SMLoc(), SMLoc()));
|
|
EmitLEA(*Op, MVT::i64, X86::RSP, Out);
|
|
OrigSPOffset += Offset;
|
|
}
|
|
|
|
void EmitCallAsanReport(unsigned AccessSize, bool IsWrite, MCContext &Ctx,
|
|
MCStreamer &Out, const RegisterContext &RegCtx) {
|
|
EmitInstruction(Out, MCInstBuilder(X86::CLD));
|
|
EmitInstruction(Out, MCInstBuilder(X86::MMX_EMMS));
|
|
|
|
EmitInstruction(Out, MCInstBuilder(X86::AND64ri8)
|
|
.addReg(X86::RSP)
|
|
.addReg(X86::RSP)
|
|
.addImm(-16));
|
|
|
|
if (RegCtx.AddressReg(MVT::i64) != X86::RDI) {
|
|
EmitInstruction(Out, MCInstBuilder(X86::MOV64rr).addReg(X86::RDI).addReg(
|
|
RegCtx.AddressReg(MVT::i64)));
|
|
}
|
|
const std::string &Fn = FuncName(AccessSize, IsWrite);
|
|
MCSymbol *FnSym = Ctx.GetOrCreateSymbol(StringRef(Fn));
|
|
const MCSymbolRefExpr *FnExpr =
|
|
MCSymbolRefExpr::Create(FnSym, MCSymbolRefExpr::VK_PLT, Ctx);
|
|
EmitInstruction(Out, MCInstBuilder(X86::CALL64pcrel32).addExpr(FnExpr));
|
|
}
|
|
};
|
|
|
|
void X86AddressSanitizer64::InstrumentMemOperandSmall(
|
|
X86Operand &Op, unsigned AccessSize, bool IsWrite,
|
|
const RegisterContext &RegCtx, MCContext &Ctx, MCStreamer &Out) {
|
|
unsigned AddressRegI64 = RegCtx.AddressReg(MVT::i64);
|
|
unsigned AddressRegI32 = RegCtx.AddressReg(MVT::i32);
|
|
unsigned ShadowRegI64 = RegCtx.ShadowReg(MVT::i64);
|
|
unsigned ShadowRegI32 = RegCtx.ShadowReg(MVT::i32);
|
|
unsigned ShadowRegI8 = RegCtx.ShadowReg(MVT::i8);
|
|
|
|
assert(RegCtx.ScratchReg(MVT::i32) != X86::NoRegister);
|
|
unsigned ScratchRegI32 = RegCtx.ScratchReg(MVT::i32);
|
|
|
|
ComputeMemOperandAddress(Op, MVT::i64, AddressRegI64, Ctx, Out);
|
|
|
|
EmitInstruction(Out, MCInstBuilder(X86::MOV64rr).addReg(ShadowRegI64).addReg(
|
|
AddressRegI64));
|
|
EmitInstruction(Out, MCInstBuilder(X86::SHR64ri)
|
|
.addReg(ShadowRegI64)
|
|
.addReg(ShadowRegI64)
|
|
.addImm(3));
|
|
{
|
|
MCInst Inst;
|
|
Inst.setOpcode(X86::MOV8rm);
|
|
Inst.addOperand(MCOperand::CreateReg(ShadowRegI8));
|
|
const MCExpr *Disp = MCConstantExpr::Create(kShadowOffset, Ctx);
|
|
std::unique_ptr<X86Operand> Op(
|
|
X86Operand::CreateMem(0, Disp, ShadowRegI64, 0, 1, SMLoc(), SMLoc()));
|
|
Op->addMemOperands(Inst, 5);
|
|
EmitInstruction(Out, Inst);
|
|
}
|
|
|
|
EmitInstruction(
|
|
Out, MCInstBuilder(X86::TEST8rr).addReg(ShadowRegI8).addReg(ShadowRegI8));
|
|
MCSymbol *DoneSym = Ctx.CreateTempSymbol();
|
|
const MCExpr *DoneExpr = MCSymbolRefExpr::Create(DoneSym, Ctx);
|
|
EmitInstruction(Out, MCInstBuilder(X86::JE_4).addExpr(DoneExpr));
|
|
|
|
EmitInstruction(Out, MCInstBuilder(X86::MOV32rr).addReg(ScratchRegI32).addReg(
|
|
AddressRegI32));
|
|
EmitInstruction(Out, MCInstBuilder(X86::AND32ri)
|
|
.addReg(ScratchRegI32)
|
|
.addReg(ScratchRegI32)
|
|
.addImm(7));
|
|
|
|
switch (AccessSize) {
|
|
case 1:
|
|
break;
|
|
case 2: {
|
|
const MCExpr *Disp = MCConstantExpr::Create(1, Ctx);
|
|
std::unique_ptr<X86Operand> Op(
|
|
X86Operand::CreateMem(0, Disp, ScratchRegI32, 0, 1, SMLoc(), SMLoc()));
|
|
EmitLEA(*Op, MVT::i32, ScratchRegI32, Out);
|
|
break;
|
|
}
|
|
case 4:
|
|
EmitInstruction(Out, MCInstBuilder(X86::ADD32ri8)
|
|
.addReg(ScratchRegI32)
|
|
.addReg(ScratchRegI32)
|
|
.addImm(3));
|
|
break;
|
|
default:
|
|
assert(false && "Incorrect access size");
|
|
break;
|
|
}
|
|
|
|
EmitInstruction(
|
|
Out,
|
|
MCInstBuilder(X86::MOVSX32rr8).addReg(ShadowRegI32).addReg(ShadowRegI8));
|
|
EmitInstruction(Out, MCInstBuilder(X86::CMP32rr).addReg(ScratchRegI32).addReg(
|
|
ShadowRegI32));
|
|
EmitInstruction(Out, MCInstBuilder(X86::JL_4).addExpr(DoneExpr));
|
|
|
|
EmitCallAsanReport(AccessSize, IsWrite, Ctx, Out, RegCtx);
|
|
EmitLabel(Out, DoneSym);
|
|
}
|
|
|
|
void X86AddressSanitizer64::InstrumentMemOperandLarge(
|
|
X86Operand &Op, unsigned AccessSize, bool IsWrite,
|
|
const RegisterContext &RegCtx, MCContext &Ctx, MCStreamer &Out) {
|
|
unsigned AddressRegI64 = RegCtx.AddressReg(MVT::i64);
|
|
unsigned ShadowRegI64 = RegCtx.ShadowReg(MVT::i64);
|
|
|
|
ComputeMemOperandAddress(Op, MVT::i64, AddressRegI64, Ctx, Out);
|
|
|
|
EmitInstruction(Out, MCInstBuilder(X86::MOV64rr).addReg(ShadowRegI64).addReg(
|
|
AddressRegI64));
|
|
EmitInstruction(Out, MCInstBuilder(X86::SHR64ri)
|
|
.addReg(ShadowRegI64)
|
|
.addReg(ShadowRegI64)
|
|
.addImm(3));
|
|
{
|
|
MCInst Inst;
|
|
switch (AccessSize) {
|
|
case 8:
|
|
Inst.setOpcode(X86::CMP8mi);
|
|
break;
|
|
case 16:
|
|
Inst.setOpcode(X86::CMP16mi);
|
|
break;
|
|
default:
|
|
assert(false && "Incorrect access size");
|
|
break;
|
|
}
|
|
const MCExpr *Disp = MCConstantExpr::Create(kShadowOffset, Ctx);
|
|
std::unique_ptr<X86Operand> Op(
|
|
X86Operand::CreateMem(0, Disp, ShadowRegI64, 0, 1, SMLoc(), SMLoc()));
|
|
Op->addMemOperands(Inst, 5);
|
|
Inst.addOperand(MCOperand::CreateImm(0));
|
|
EmitInstruction(Out, Inst);
|
|
}
|
|
|
|
MCSymbol *DoneSym = Ctx.CreateTempSymbol();
|
|
const MCExpr *DoneExpr = MCSymbolRefExpr::Create(DoneSym, Ctx);
|
|
EmitInstruction(Out, MCInstBuilder(X86::JE_4).addExpr(DoneExpr));
|
|
|
|
EmitCallAsanReport(AccessSize, IsWrite, Ctx, Out, RegCtx);
|
|
EmitLabel(Out, DoneSym);
|
|
}
|
|
|
|
void X86AddressSanitizer64::InstrumentMOVSImpl(unsigned AccessSize,
|
|
MCContext &Ctx,
|
|
MCStreamer &Out) {
|
|
StoreFlags(Out);
|
|
|
|
// No need to test when RCX is equals to zero.
|
|
MCSymbol *DoneSym = Ctx.CreateTempSymbol();
|
|
const MCExpr *DoneExpr = MCSymbolRefExpr::Create(DoneSym, Ctx);
|
|
EmitInstruction(
|
|
Out, MCInstBuilder(X86::TEST64rr).addReg(X86::RCX).addReg(X86::RCX));
|
|
EmitInstruction(Out, MCInstBuilder(X86::JE_4).addExpr(DoneExpr));
|
|
|
|
// Instrument first and last elements in src and dst range.
|
|
InstrumentMOVSBase(X86::RDI /* DstReg */, X86::RSI /* SrcReg */,
|
|
X86::RCX /* CntReg */, AccessSize, Ctx, Out);
|
|
|
|
EmitLabel(Out, DoneSym);
|
|
RestoreFlags(Out);
|
|
}
|
|
|
|
} // End anonymous namespace
|
|
|
|
X86AsmInstrumentation::X86AsmInstrumentation(const MCSubtargetInfo &STI)
|
|
: STI(STI), InitialFrameReg(0) {}
|
|
|
|
X86AsmInstrumentation::~X86AsmInstrumentation() {}
|
|
|
|
void X86AsmInstrumentation::InstrumentAndEmitInstruction(
|
|
const MCInst &Inst, OperandVector &Operands, MCContext &Ctx,
|
|
const MCInstrInfo &MII, MCStreamer &Out) {
|
|
EmitInstruction(Out, Inst);
|
|
}
|
|
|
|
void X86AsmInstrumentation::EmitInstruction(MCStreamer &Out,
|
|
const MCInst &Inst) {
|
|
Out.EmitInstruction(Inst, STI);
|
|
}
|
|
|
|
unsigned X86AsmInstrumentation::GetFrameRegGeneric(const MCContext &Ctx,
|
|
MCStreamer &Out) {
|
|
if (!Out.getNumFrameInfos()) // No active dwarf frame
|
|
return X86::NoRegister;
|
|
const MCDwarfFrameInfo &Frame = Out.getDwarfFrameInfos().back();
|
|
if (Frame.End) // Active dwarf frame is closed
|
|
return X86::NoRegister;
|
|
const MCRegisterInfo *MRI = Ctx.getRegisterInfo();
|
|
if (!MRI) // No register info
|
|
return X86::NoRegister;
|
|
|
|
if (InitialFrameReg) {
|
|
// FrameReg is set explicitly, we're instrumenting a MachineFunction.
|
|
return InitialFrameReg;
|
|
}
|
|
|
|
return MRI->getLLVMRegNum(Frame.CurrentCfaRegister, true /* IsEH */);
|
|
}
|
|
|
|
X86AsmInstrumentation *
|
|
CreateX86AsmInstrumentation(const MCTargetOptions &MCOptions,
|
|
const MCContext &Ctx, const MCSubtargetInfo &STI) {
|
|
Triple T(STI.getTargetTriple());
|
|
const bool hasCompilerRTSupport = T.isOSLinux();
|
|
if (ClAsanInstrumentAssembly && hasCompilerRTSupport &&
|
|
MCOptions.SanitizeAddress) {
|
|
if ((STI.getFeatureBits() & X86::Mode32Bit) != 0)
|
|
return new X86AddressSanitizer32(STI);
|
|
if ((STI.getFeatureBits() & X86::Mode64Bit) != 0)
|
|
return new X86AddressSanitizer64(STI);
|
|
}
|
|
return new X86AsmInstrumentation(STI);
|
|
}
|
|
|
|
} // End llvm namespace
|