Jim Grosbach be7cf2b377 ARM ldm/stm register lists can be out of order. ...

It's not a good style idea, as the registers will be laid down in memory in
numerical order, not the order they're in the list, but it's legal. vldm/vstm
are stricter.

rdar://11064740

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152943 91177308-0d34-0410-b5e6-96231b3b80d8

2012-03-16 20:48:38 +00:00

..

Analysis

Start removing the use of an ad-hoc 'never inline' set and instead

2012-03-16 06:10:13 +00:00

Archive

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AsmParser

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Bitcode

llvm::SwitchInst

2012-03-11 06:09:17 +00:00

CodeGen

ScheduleDAGInstrs: When adding uses we add them into a set that's empty at the beginning, no need to maintain another set for the added regs.

2012-03-16 17:38:19 +00:00

DebugInfo

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ExecutionEngine

Add profiling support for Intel Parallel Amplifier XE (VTune) for JITted code in LLVM.

2012-03-13 08:33:15 +00:00

Linker

Include cctype for isdigit. Patch by Stephen Hines.

2012-03-03 09:36:58 +00:00

MC

Implement relocation-overflow behavior for PE/COFF.

2012-03-15 09:03:03 +00:00

Object

Fix bug found by warning.

2012-03-15 17:49:29 +00:00

Support

Move APInt::operator[] inline.

2012-03-14 00:38:15 +00:00

TableGen

Fix infinite loop in nested multiclasses.

2012-03-07 16:39:35 +00:00

Target

ARM ldm/stm register lists can be out of order.

2012-03-16 20:48:38 +00:00

Transforms

Revert r152907.

2012-03-16 18:20:54 +00:00

VMCore

Extend the inline cost calculation to account for bonuses due to

2012-03-14 23:19:53 +00:00

CMakeLists.txt

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LLVMBuild.txt

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Makefile

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