Tom Stellard bfffad69b2 R600/SI: Use VALU instructions for i1 ops ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208885 91177308-0d34-0410-b5e6-96231b3b80d8

2014-05-15 14:41:50 +00:00

..

AArch64

ARM64: print correct aliases for NEON mov & mvn instructions

2014-05-15 12:11:02 +00:00

ARM

Rename ComputeMaskedBits to computeKnownBits. "Masked" has been

2014-05-14 21:14:37 +00:00

ARM64

ARM64: print correct aliases for NEON mov & mvn instructions

2014-05-15 12:11:02 +00:00

CPP

Begin adding docs and IR-level support for the inalloca attribute

2013-12-19 02:14:12 +00:00

Generic

MC: move test from Generic to COFF

2014-04-23 21:41:07 +00:00

Hexagon

DebugInfo: Sure up subprogram variable list handling with more assertions and fewer conditionals.

2014-05-14 21:52:46 +00:00

Inputs

…

Mips

Allow sret on the second parameter as well as the first

2014-05-09 22:32:13 +00:00

MSP430

Mark FPB as a reserved register when needed.

2014-04-02 13:13:56 +00:00

NVPTX

Fix the test: DCE optimized away everything.

2014-04-21 17:23:12 +00:00

PowerPC

DebugInfo: Sure up subprogram variable list handling with more assertions and fewer conditionals.

2014-05-14 21:52:46 +00:00

R600

R600/SI: Use VALU instructions for i1 ops

2014-05-15 14:41:50 +00:00

SPARC

Allow sret on the second parameter as well as the first

2014-05-09 22:32:13 +00:00

SystemZ

Reenable use of TBAA during CodeGen

2014-04-12 01:26:00 +00:00

Thumb

Make this test not match its own filename, when being run from a path that includes the string 'add'.

2014-04-15 22:29:32 +00:00

Thumb2

Move the segmented stack switch to a function attribute

2014-04-10 22:58:43 +00:00

X86

Rename ComputeMaskedBits to computeKnownBits. "Masked" has been

2014-05-14 21:14:37 +00:00

XCore

Reapply "blockfreq: Rewrite BlockFrequencyInfoImpl"

2014-04-21 17:57:07 +00:00