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https://github.com/c64scene-ar/llvm-6502.git
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d68a07650c
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61715 91177308-0d34-0410-b5e6-96231b3b80d8
470 lines
17 KiB
C++
470 lines
17 KiB
C++
//===-- TwoAddressInstructionPass.cpp - Two-Address instruction pass ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the TwoAddress instruction pass which is used
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// by most register allocators. Two-Address instructions are rewritten
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// from:
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//
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// A = B op C
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//
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// to:
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//
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// A = B
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// A op= C
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//
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// Note that if a register allocator chooses to use this pass, that it
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// has to be capable of handling the non-SSA nature of these rewritten
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// virtual registers.
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//
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// It is also worth noting that the duplicate operand of the two
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// address instruction is removed.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "twoaddrinstr"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/STLExtras.h"
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using namespace llvm;
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STATISTIC(NumTwoAddressInstrs, "Number of two-address instructions");
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STATISTIC(NumCommuted , "Number of instructions commuted to coalesce");
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STATISTIC(NumConvertedTo3Addr, "Number of instructions promoted to 3-address");
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STATISTIC(Num3AddrSunk, "Number of 3-address instructions sunk");
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STATISTIC(NumReMats, "Number of instructions re-materialized");
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namespace {
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class VISIBILITY_HIDDEN TwoAddressInstructionPass
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: public MachineFunctionPass {
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const TargetInstrInfo *TII;
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const TargetRegisterInfo *TRI;
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MachineRegisterInfo *MRI;
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LiveVariables *LV;
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bool Sink3AddrInstruction(MachineBasicBlock *MBB, MachineInstr *MI,
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unsigned Reg,
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MachineBasicBlock::iterator OldPos);
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bool isProfitableToReMat(unsigned Reg, const TargetRegisterClass *RC,
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MachineInstr *MI, MachineInstr *DefMI,
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MachineBasicBlock *MBB, unsigned Loc,
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DenseMap<MachineInstr*, unsigned> &DistanceMap);
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public:
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static char ID; // Pass identification, replacement for typeid
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TwoAddressInstructionPass() : MachineFunctionPass(&ID) {}
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addPreserved<LiveVariables>();
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AU.addPreservedID(MachineLoopInfoID);
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AU.addPreservedID(MachineDominatorsID);
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if (StrongPHIElim)
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AU.addPreservedID(StrongPHIEliminationID);
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else
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AU.addPreservedID(PHIEliminationID);
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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/// runOnMachineFunction - Pass entry point.
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bool runOnMachineFunction(MachineFunction&);
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};
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}
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char TwoAddressInstructionPass::ID = 0;
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static RegisterPass<TwoAddressInstructionPass>
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X("twoaddressinstruction", "Two-Address instruction pass");
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const PassInfo *const llvm::TwoAddressInstructionPassID = &X;
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/// Sink3AddrInstruction - A two-address instruction has been converted to a
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/// three-address instruction to avoid clobbering a register. Try to sink it
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/// past the instruction that would kill the above mentioned register to reduce
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/// register pressure.
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bool TwoAddressInstructionPass::Sink3AddrInstruction(MachineBasicBlock *MBB,
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MachineInstr *MI, unsigned SavedReg,
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MachineBasicBlock::iterator OldPos) {
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// Check if it's safe to move this instruction.
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bool SeenStore = true; // Be conservative.
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if (!MI->isSafeToMove(TII, SeenStore))
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return false;
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unsigned DefReg = 0;
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SmallSet<unsigned, 4> UseRegs;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg())
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continue;
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unsigned MOReg = MO.getReg();
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if (!MOReg)
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continue;
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if (MO.isUse() && MOReg != SavedReg)
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UseRegs.insert(MO.getReg());
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if (!MO.isDef())
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continue;
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if (MO.isImplicit())
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// Don't try to move it if it implicitly defines a register.
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return false;
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if (DefReg)
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// For now, don't move any instructions that define multiple registers.
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return false;
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DefReg = MO.getReg();
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}
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// Find the instruction that kills SavedReg.
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MachineInstr *KillMI = NULL;
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for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SavedReg),
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UE = MRI->use_end(); UI != UE; ++UI) {
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MachineOperand &UseMO = UI.getOperand();
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if (!UseMO.isKill())
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continue;
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KillMI = UseMO.getParent();
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break;
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}
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if (!KillMI || KillMI->getParent() != MBB)
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return false;
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// If any of the definitions are used by another instruction between the
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// position and the kill use, then it's not safe to sink it.
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//
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// FIXME: This can be sped up if there is an easy way to query whether an
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// instruction is before or after another instruction. Then we can use
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// MachineRegisterInfo def / use instead.
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MachineOperand *KillMO = NULL;
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MachineBasicBlock::iterator KillPos = KillMI;
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++KillPos;
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unsigned NumVisited = 0;
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for (MachineBasicBlock::iterator I = next(OldPos); I != KillPos; ++I) {
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MachineInstr *OtherMI = I;
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if (NumVisited > 30) // FIXME: Arbitrary limit to reduce compile time cost.
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return false;
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++NumVisited;
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for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = OtherMI->getOperand(i);
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if (!MO.isReg())
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continue;
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unsigned MOReg = MO.getReg();
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if (!MOReg)
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continue;
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if (DefReg == MOReg)
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return false;
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if (MO.isKill()) {
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if (OtherMI == KillMI && MOReg == SavedReg)
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// Save the operand that kills the register. We want to unset the kill
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// marker if we can sink MI past it.
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KillMO = &MO;
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else if (UseRegs.count(MOReg))
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// One of the uses is killed before the destination.
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return false;
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}
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}
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}
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// Update kill and LV information.
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KillMO->setIsKill(false);
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KillMO = MI->findRegisterUseOperand(SavedReg, false, TRI);
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KillMO->setIsKill(true);
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if (LV)
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LV->replaceKillInstruction(SavedReg, KillMI, MI);
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// Move instruction to its destination.
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MBB->remove(MI);
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MBB->insert(KillPos, MI);
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++Num3AddrSunk;
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return true;
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}
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/// isTwoAddrUse - Return true if the specified MI is using the specified
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/// register as a two-address operand.
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static bool isTwoAddrUse(MachineInstr *UseMI, unsigned Reg) {
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const TargetInstrDesc &TID = UseMI->getDesc();
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for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
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MachineOperand &MO = UseMI->getOperand(i);
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if (MO.isReg() && MO.getReg() == Reg &&
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(MO.isDef() || TID.getOperandConstraint(i, TOI::TIED_TO) != -1))
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// Earlier use is a two-address one.
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return true;
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}
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return false;
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}
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/// isProfitableToReMat - Return true if the heuristics determines it is likely
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/// to be profitable to re-materialize the definition of Reg rather than copy
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/// the register.
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bool
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TwoAddressInstructionPass::isProfitableToReMat(unsigned Reg,
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const TargetRegisterClass *RC,
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MachineInstr *MI, MachineInstr *DefMI,
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MachineBasicBlock *MBB, unsigned Loc,
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DenseMap<MachineInstr*, unsigned> &DistanceMap){
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bool OtherUse = false;
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for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg),
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UE = MRI->use_end(); UI != UE; ++UI) {
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MachineOperand &UseMO = UI.getOperand();
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if (!UseMO.isUse())
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continue;
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MachineInstr *UseMI = UseMO.getParent();
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MachineBasicBlock *UseMBB = UseMI->getParent();
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if (UseMBB == MBB) {
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DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI);
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if (DI != DistanceMap.end() && DI->second == Loc)
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continue; // Current use.
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OtherUse = true;
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// There is at least one other use in the MBB that will clobber the
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// register.
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if (isTwoAddrUse(UseMI, Reg))
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return true;
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}
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}
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// If other uses in MBB are not two-address uses, then don't remat.
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if (OtherUse)
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return false;
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// No other uses in the same block, remat if it's defined in the same
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// block so it does not unnecessarily extend the live range.
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return MBB == DefMI->getParent();
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}
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/// runOnMachineFunction - Reduce two-address instructions to two operands.
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///
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bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
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DOUT << "Machine Function\n";
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const TargetMachine &TM = MF.getTarget();
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MRI = &MF.getRegInfo();
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TII = TM.getInstrInfo();
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TRI = TM.getRegisterInfo();
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LV = getAnalysisToUpdate<LiveVariables>();
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bool MadeChange = false;
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DOUT << "********** REWRITING TWO-ADDR INSTRS **********\n";
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DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
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// ReMatRegs - Keep track of the registers whose def's are remat'ed.
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BitVector ReMatRegs;
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ReMatRegs.resize(MRI->getLastVirtReg()+1);
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// DistanceMap - Keep track the distance of a MI from the start of the
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// current basic block.
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DenseMap<MachineInstr*, unsigned> DistanceMap;
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for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
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mbbi != mbbe; ++mbbi) {
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unsigned Dist = 0;
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DistanceMap.clear();
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for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
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mi != me; ) {
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MachineBasicBlock::iterator nmi = next(mi);
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const TargetInstrDesc &TID = mi->getDesc();
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bool FirstTied = true;
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DistanceMap.insert(std::make_pair(mi, ++Dist));
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for (unsigned si = 1, e = TID.getNumOperands(); si < e; ++si) {
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int ti = TID.getOperandConstraint(si, TOI::TIED_TO);
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if (ti == -1)
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continue;
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if (FirstTied) {
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++NumTwoAddressInstrs;
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DOUT << '\t'; DEBUG(mi->print(*cerr.stream(), &TM));
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}
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FirstTied = false;
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assert(mi->getOperand(si).isReg() && mi->getOperand(si).getReg() &&
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mi->getOperand(si).isUse() && "two address instruction invalid");
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// If the two operands are the same we just remove the use
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// and mark the def as def&use, otherwise we have to insert a copy.
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if (mi->getOperand(ti).getReg() != mi->getOperand(si).getReg()) {
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// Rewrite:
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// a = b op c
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// to:
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// a = b
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// a = a op c
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unsigned regA = mi->getOperand(ti).getReg();
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unsigned regB = mi->getOperand(si).getReg();
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assert(TargetRegisterInfo::isVirtualRegister(regA) &&
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TargetRegisterInfo::isVirtualRegister(regB) &&
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"cannot update physical register live information");
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#ifndef NDEBUG
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// First, verify that we don't have a use of a in the instruction (a =
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// b + a for example) because our transformation will not work. This
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// should never occur because we are in SSA form.
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for (unsigned i = 0; i != mi->getNumOperands(); ++i)
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assert((int)i == ti ||
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!mi->getOperand(i).isReg() ||
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mi->getOperand(i).getReg() != regA);
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#endif
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// If this instruction is not the killing user of B, see if we can
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// rearrange the code to make it so. Making it the killing user will
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// allow us to coalesce A and B together, eliminating the copy we are
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// about to insert.
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if (!mi->killsRegister(regB)) {
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// If this instruction is commutative, check to see if C dies. If
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// so, swap the B and C operands. This makes the live ranges of A
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// and C joinable.
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// FIXME: This code also works for A := B op C instructions.
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if (TID.isCommutable() && mi->getNumOperands() >= 3) {
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assert(mi->getOperand(3-si).isReg() &&
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"Not a proper commutative instruction!");
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unsigned regC = mi->getOperand(3-si).getReg();
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if (mi->killsRegister(regC)) {
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DOUT << "2addr: COMMUTING : " << *mi;
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MachineInstr *NewMI = TII->commuteInstruction(mi);
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if (NewMI == 0) {
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DOUT << "2addr: COMMUTING FAILED!\n";
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} else {
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DOUT << "2addr: COMMUTED TO: " << *NewMI;
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// If the instruction changed to commute it, update livevar.
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if (NewMI != mi) {
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if (LV)
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// Update live variables
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LV->replaceKillInstruction(regC, mi, NewMI);
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mbbi->insert(mi, NewMI); // Insert the new inst
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mbbi->erase(mi); // Nuke the old inst.
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mi = NewMI;
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DistanceMap.insert(std::make_pair(NewMI, Dist));
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}
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++NumCommuted;
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regB = regC;
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goto InstructionRearranged;
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}
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}
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}
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// If this instruction is potentially convertible to a true
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// three-address instruction,
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if (TID.isConvertibleTo3Addr()) {
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// FIXME: This assumes there are no more operands which are tied
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// to another register.
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#ifndef NDEBUG
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for (unsigned i = si + 1, e = TID.getNumOperands(); i < e; ++i)
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assert(TID.getOperandConstraint(i, TOI::TIED_TO) == -1);
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#endif
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MachineInstr *NewMI = TII->convertToThreeAddress(mbbi, mi, LV);
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if (NewMI) {
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DOUT << "2addr: CONVERTING 2-ADDR: " << *mi;
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DOUT << "2addr: TO 3-ADDR: " << *NewMI;
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bool Sunk = false;
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if (NewMI->findRegisterUseOperand(regB, false, TRI))
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// FIXME: Temporary workaround. If the new instruction doesn't
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// uses regB, convertToThreeAddress must have created more
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// then one instruction.
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Sunk = Sink3AddrInstruction(mbbi, NewMI, regB, mi);
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mbbi->erase(mi); // Nuke the old inst.
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if (!Sunk) {
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DistanceMap.insert(std::make_pair(NewMI, Dist));
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mi = NewMI;
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nmi = next(mi);
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}
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++NumConvertedTo3Addr;
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break; // Done with this instruction.
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}
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}
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}
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InstructionRearranged:
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const TargetRegisterClass* rc = MRI->getRegClass(regA);
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MachineInstr *DefMI = MRI->getVRegDef(regB);
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// If it's safe and profitable, remat the definition instead of
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// copying it.
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if (DefMI &&
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DefMI->getDesc().isAsCheapAsAMove() &&
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DefMI->isSafeToReMat(TII, regB) &&
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isProfitableToReMat(regB, rc, mi, DefMI, mbbi, Dist,DistanceMap)){
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DEBUG(cerr << "2addr: REMATTING : " << *DefMI << "\n");
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TII->reMaterialize(*mbbi, mi, regA, DefMI);
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ReMatRegs.set(regB);
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++NumReMats;
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} else {
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TII->copyRegToReg(*mbbi, mi, regA, regB, rc, rc);
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}
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MachineBasicBlock::iterator prevMi = prior(mi);
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// Update live variables for regB.
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if (LV) {
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LiveVariables::VarInfo& varInfoB = LV->getVarInfo(regB);
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// regB is used in this BB.
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varInfoB.UsedBlocks[mbbi->getNumber()] = true;
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if (LV->removeVirtualRegisterKilled(regB, mi))
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LV->addVirtualRegisterKilled(regB, prevMi);
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if (LV->removeVirtualRegisterDead(regB, mi))
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LV->addVirtualRegisterDead(regB, prevMi);
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}
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DOUT << "\t\tprepend:\t"; DEBUG(prevMi->print(*cerr.stream(), &TM));
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// Replace all occurences of regB with regA.
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for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) {
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if (mi->getOperand(i).isReg() &&
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mi->getOperand(i).getReg() == regB)
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mi->getOperand(i).setReg(regA);
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}
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}
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assert(mi->getOperand(ti).isDef() && mi->getOperand(si).isUse());
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mi->getOperand(ti).setReg(mi->getOperand(si).getReg());
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MadeChange = true;
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DOUT << "\t\trewrite to:\t"; DEBUG(mi->print(*cerr.stream(), &TM));
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}
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mi = nmi;
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}
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}
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// Some remat'ed instructions are dead.
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int VReg = ReMatRegs.find_first();
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while (VReg != -1) {
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if (MRI->use_empty(VReg)) {
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MachineInstr *DefMI = MRI->getVRegDef(VReg);
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DefMI->eraseFromParent();
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}
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VReg = ReMatRegs.find_next(VReg);
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}
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return MadeChange;
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}
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