Matt Arsenault 6a72b20325 R600/SI: Add combine for isinfinite pattern ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225310 91177308-0d34-0410-b5e6-96231b3b80d8

2015-01-06 23:00:46 +00:00

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AArch64

[AArch64] Improve codegen of store lane instructions by avoiding GPR usage.

2015-01-05 17:10:26 +00:00

ARM

Emit the build attribute Tag_conformance.

2015-01-05 13:12:17 +00:00

CPP

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Generic

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Hexagon

[Hexagon] Adding dealloc_return encoding and absolute address stores.

2015-01-06 16:15:15 +00:00

Inputs

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Mips

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MSP430

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NVPTX

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PowerPC

[PowerPC] Reuse a load operand in int->fp conversions

2015-01-06 22:31:02 +00:00

R600

R600/SI: Add combine for isinfinite pattern

2015-01-06 23:00:46 +00:00

SPARC

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SystemZ

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Thumb

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Thumb2

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X86

Change the .ll syntax for comdats and add a syntactic sugar.

2015-01-06 22:55:16 +00:00

XCore

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