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llvm-6502/lib/Target
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Duraid Madina c1d3d10249 support functions that return bool (this "should" work but doesn't, 
*maybe* due to a legalizer bug.)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25171 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-10 05:08:25 +00:00
..
Alpha
proper branch not equal sequence
2006-01-09 19:49:58 +00:00
CBackend
yet more C++ standards-compliance stuff.
2005-12-27 10:40:34 +00:00
IA64
support functions that return bool (this "should" work but doesn't,
2006-01-10 05:08:25 +00:00
PowerPC
Remove a comment that no longer applies.
2006-01-10 00:15:59 +00:00
Skeleton
Support multiple ValueTypes per RegisterClass, needed for upcoming vector
2005-12-01 04:51:06 +00:00
Sparc
New DAG node properties SNDPInFlag, SNDPOutFlag, and SNDPOptInFlag to replace
2006-01-09 18:28:21 +00:00
SparcV8
New DAG node properties SNDPInFlag, SNDPOutFlag, and SNDPOptInFlag to replace
2006-01-09 18:28:21 +00:00
SparcV9
Support multiple ValueTypes per RegisterClass, needed for upcoming vector
2005-12-01 04:51:06 +00:00
X86
* Added undef patterns.
2006-01-09 23:10:28 +00:00
Makefile
DONT_BUILD_RELINKED is gone and implied by BUILD_ARCHIVE now
2005-10-24 02:26:13 +00:00
MRegisterInfo.cpp
Rename MRegisterDesc -> TargetRegisterDesc for consistency
2005-09-30 17:49:27 +00:00
SubtargetFeature.cpp
Preparation of supporting scheduling info. Need to find info based on selected
2005-10-25 15:15:28 +00:00
Target.td
New DAG node properties SNDPInFlag, SNDPOutFlag, and SNDPOptInFlag to replace
2006-01-09 18:28:21 +00:00
TargetData.cpp
…
TargetFrameInfo.cpp
…
TargetInstrInfo.cpp
…
TargetMachine.cpp
Remove the X86 and PowerPC Simple instruction selectors; their time has
2005-08-18 23:53:15 +00:00
TargetMachineRegistry.cpp
1. Use SubtargetFeatures in llc/lli.
2005-09-01 21:38:21 +00:00
TargetSchedInfo.cpp
…
TargetSchedule.td
add a marker
2005-10-23 22:07:20 +00:00
TargetSelectionDAG.td
New DAG node properties SNDPInFlag, SNDPOutFlag, and SNDPOptInFlag to replace
2006-01-09 18:28:21 +00:00
TargetSubtarget.cpp
…