mirror of
https://github.com/c64scene-ar/llvm-6502.git
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d68e8cda24
It is redundant; RegisterCoalescer will do the remat if it can't eliminate the copy. Collected instruction counts before and after this. A few extra instructions are generated due to spilling but it is normal to see these kinds of changes with almost any small codegen change, according to Jakob. This also fixed rdar://11830760 where xor is expected instead of movi0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160749 91177308-0d34-0410-b5e6-96231b3b80d8
217 lines
4.8 KiB
LLVM
217 lines
4.8 KiB
LLVM
; RUN: llc < %s -march=x86 -mcpu=pentiumpro | FileCheck %s
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define i32 @f(i32 %X) {
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entry:
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; CHECK: f:
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; CHECK: jns
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%tmp1 = add i32 %X, 1 ; <i32> [#uses=1]
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%tmp = icmp slt i32 %tmp1, 0 ; <i1> [#uses=1]
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br i1 %tmp, label %cond_true, label %cond_next
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cond_true: ; preds = %entry
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%tmp2 = tail call i32 (...)* @bar( ) ; <i32> [#uses=0]
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br label %cond_next
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cond_next: ; preds = %cond_true, %entry
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%tmp3 = tail call i32 (...)* @baz( ) ; <i32> [#uses=0]
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ret i32 undef
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}
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declare i32 @bar(...)
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declare i32 @baz(...)
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; rdar://10633221
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; rdar://11355268
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define i32 @g(i32 %a, i32 %b) nounwind {
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entry:
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; CHECK: g:
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; CHECK-NOT: test
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; CHECK: cmovs
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%sub = sub nsw i32 %a, %b
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%cmp = icmp sgt i32 %sub, 0
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%cond = select i1 %cmp, i32 %sub, i32 0
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ret i32 %cond
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}
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; rdar://10734411
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define i32 @h(i32 %a, i32 %b) nounwind {
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entry:
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; CHECK: h:
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; CHECK-NOT: cmp
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; CHECK: cmov
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; CHECK-NOT: movl
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; CHECK: ret
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%cmp = icmp slt i32 %b, %a
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%sub = sub nsw i32 %a, %b
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%cond = select i1 %cmp, i32 %sub, i32 0
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ret i32 %cond
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}
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define i32 @i(i32 %a, i32 %b) nounwind {
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entry:
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; CHECK: i:
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; CHECK-NOT: cmp
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; CHECK: cmov
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; CHECK-NOT: movl
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; CHECK: ret
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%cmp = icmp sgt i32 %a, %b
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%sub = sub nsw i32 %a, %b
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%cond = select i1 %cmp, i32 %sub, i32 0
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ret i32 %cond
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}
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define i32 @j(i32 %a, i32 %b) nounwind {
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entry:
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; CHECK: j:
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; CHECK-NOT: cmp
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; CHECK: cmov
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; CHECK-NOT: movl
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; CHECK: ret
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%cmp = icmp ugt i32 %a, %b
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%sub = sub i32 %a, %b
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%cond = select i1 %cmp, i32 %sub, i32 0
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ret i32 %cond
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}
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define i32 @k(i32 %a, i32 %b) nounwind {
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entry:
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; CHECK: k:
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; CHECK-NOT: cmp
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; CHECK: cmov
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; CHECK-NOT: movl
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; CHECK: ret
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%cmp = icmp ult i32 %b, %a
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%sub = sub i32 %a, %b
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%cond = select i1 %cmp, i32 %sub, i32 0
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ret i32 %cond
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}
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; redundant cmp instruction
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define i32 @l(i32 %a, i32 %b) nounwind {
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entry:
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; CHECK: l:
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; CHECK-NOT: cmp
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%cmp = icmp slt i32 %b, %a
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%sub = sub nsw i32 %a, %b
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%cond = select i1 %cmp, i32 %sub, i32 %a
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ret i32 %cond
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}
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define i32 @m(i32 %a, i32 %b) nounwind {
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entry:
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; CHECK: m:
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; CHECK-NOT: cmp
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%cmp = icmp sgt i32 %a, %b
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%sub = sub nsw i32 %a, %b
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%cond = select i1 %cmp, i32 %b, i32 %sub
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ret i32 %cond
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}
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; If EFLAGS is live-out, we can't remove cmp if there exists
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; a swapped sub.
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define i32 @l2(i32 %a, i32 %b) nounwind {
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entry:
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; CHECK: l2:
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; CHECK: cmp
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%cmp = icmp eq i32 %b, %a
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%sub = sub nsw i32 %a, %b
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br i1 %cmp, label %if.then, label %if.else
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if.then:
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%cmp2 = icmp sgt i32 %b, %a
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%sel = select i1 %cmp2, i32 %sub, i32 %a
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ret i32 %sel
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if.else:
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ret i32 %sub
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}
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define i32 @l3(i32 %a, i32 %b) nounwind {
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entry:
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; CHECK: l3:
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; CHECK: sub
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; CHECK-NOT: cmp
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; CHECK: jge
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%cmp = icmp sgt i32 %b, %a
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%sub = sub nsw i32 %a, %b
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br i1 %cmp, label %if.then, label %if.else
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if.then:
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ret i32 %sub
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if.else:
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%add = add nsw i32 %sub, 1
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ret i32 %add
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}
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; rdar://11830760
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; When Movr0 is between sub and cmp, we need to move "Movr0" before sub.
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define i32 @l4(i32 %a, i32 %b) nounwind {
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entry:
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; CHECK: l4:
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; CHECK: xor
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; CHECK: sub
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; CHECK-NOT: cmp
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%cmp = icmp sgt i32 %b, %a
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%sub = sub i32 %a, %b
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%.sub = select i1 %cmp, i32 0, i32 %sub
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ret i32 %.sub
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}
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; rdar://11540023
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define i32 @n(i32 %x, i32 %y) nounwind {
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entry:
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; CHECK: n:
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; CHECK-NOT: sub
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; CHECK: cmp
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%sub = sub nsw i32 %x, %y
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%cmp = icmp slt i32 %sub, 0
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%y.x = select i1 %cmp, i32 %y, i32 %x
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ret i32 %y.x
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}
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; PR://13046
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define void @o() nounwind uwtable {
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entry:
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%0 = load i16* undef, align 2
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br i1 undef, label %if.then.i, label %if.end.i
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if.then.i: ; preds = %entry
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unreachable
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if.end.i: ; preds = %entry
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br i1 undef, label %sw.bb, label %sw.default
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sw.bb: ; preds = %if.end.i
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br i1 undef, label %if.then44, label %if.end29
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if.end29: ; preds = %sw.bb
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; CHECK: o:
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; CHECK: cmp
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%1 = urem i16 %0, 10
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%cmp25 = icmp eq i16 %1, 0
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%. = select i1 %cmp25, i16 2, i16 0
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br i1 %cmp25, label %if.then44, label %sw.default
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sw.default: ; preds = %if.end29, %if.end.i
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br i1 undef, label %if.then.i96, label %if.else.i97
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if.then.i96: ; preds = %sw.default
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unreachable
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if.else.i97: ; preds = %sw.default
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unreachable
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if.then44: ; preds = %if.end29, %sw.bb
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%aModeRefSel.1.ph = phi i16 [ %., %if.end29 ], [ 3, %sw.bb ]
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br i1 undef, label %if.then.i103, label %if.else.i104
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if.then.i103: ; preds = %if.then44
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unreachable
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if.else.i104: ; preds = %if.then44
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ret void
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}
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; rdar://11855129
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define i32 @p(i32 %a, i32 %b) nounwind {
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entry:
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; CHECK: p:
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; CHECK-NOT: test
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; CHECK: cmovs
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%add = add nsw i32 %b, %a
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%cmp = icmp sgt i32 %add, 0
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%add. = select i1 %cmp, i32 %add, i32 0
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ret i32 %add.
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}
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