llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-03 15:36:21 +00:00

History

Andrea Di Biagio c270e8abbe [X86] Add 'FeatureSlowSHLD' to cpu 'bdver3'. Also explicit set FeatureAVX and FeatureSSE4A for all the bdver* cpus.

This patch adds 'FeatureSlowSHLD' to 'bdver3'.
According to the official AMD optimization guide for amdfam15: "Using
alternative code in place of SHLD achieves lower overall latency and
requires fewer execution resources. The 32-bit and 64-bit forms of
ADD, ADC, SHR, and LEA (except 16-bit form) are DirectPath
instructions, while SHLD is a VectorPath instruction."

This patch also explicitly sets feature AVX and SSE4A for all the bdver*
cpus. This part of the patch is a non-functional change and it is mainly
done for clarity reasons (Both XOP and FMA4 already imply AVX and SSE4A).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221296 91177308-0d34-0410-b5e6-96231b3b80d8

2014-11-04 21:18:09 +00:00

Analysis

InstSimplify: Fold a hasNoSignedWrap() call into a match() expression

2014-11-04 17:47:13 +00:00

AsmParser

X86: Implement the vectorcall calling convention

2014-10-28 01:29:26 +00:00

Bitcode

IR: MDNode => Value: Instruction::getAllMetadataOtherThanDebugLoc()

2014-11-03 18:13:57 +00:00

CodeGen

[PBQP] Callee saved regs should have a higher cost than scratch regs