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representing expressions that can only be resolved at link time, etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30278 91177308-0d34-0410-b5e6-96231b3b80d8
675 lines
24 KiB
C++
675 lines
24 KiB
C++
//===---- ScheduleDAG.cpp - Implement the ScheduleDAG class ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by James M. Laskey and is distributed under the
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// University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This implements a simple two pass scheduler. The first pass attempts to push
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// backward any lengthy instructions and critical paths. The second pass packs
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// instructions into semi-optimal time slots.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "sched"
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#include "llvm/CodeGen/ScheduleDAG.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/MathExtras.h"
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#include <iostream>
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using namespace llvm;
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/// BuildSchedUnits - Build SUnits from the selection dag that we are input.
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/// This SUnit graph is similar to the SelectionDAG, but represents flagged
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/// together nodes with a single SUnit.
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void ScheduleDAG::BuildSchedUnits() {
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// Reserve entries in the vector for each of the SUnits we are creating. This
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// ensure that reallocation of the vector won't happen, so SUnit*'s won't get
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// invalidated.
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SUnits.reserve(std::distance(DAG.allnodes_begin(), DAG.allnodes_end()));
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const InstrItineraryData &InstrItins = TM.getInstrItineraryData();
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for (SelectionDAG::allnodes_iterator NI = DAG.allnodes_begin(),
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E = DAG.allnodes_end(); NI != E; ++NI) {
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if (isPassiveNode(NI)) // Leaf node, e.g. a TargetImmediate.
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continue;
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// If this node has already been processed, stop now.
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if (SUnitMap[NI]) continue;
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SUnit *NodeSUnit = NewSUnit(NI);
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// See if anything is flagged to this node, if so, add them to flagged
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// nodes. Nodes can have at most one flag input and one flag output. Flags
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// are required the be the last operand and result of a node.
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// Scan up, adding flagged preds to FlaggedNodes.
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SDNode *N = NI;
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if (N->getNumOperands() &&
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N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) {
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do {
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N = N->getOperand(N->getNumOperands()-1).Val;
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NodeSUnit->FlaggedNodes.push_back(N);
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SUnitMap[N] = NodeSUnit;
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} while (N->getNumOperands() &&
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N->getOperand(N->getNumOperands()-1).getValueType()== MVT::Flag);
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std::reverse(NodeSUnit->FlaggedNodes.begin(),
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NodeSUnit->FlaggedNodes.end());
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}
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// Scan down, adding this node and any flagged succs to FlaggedNodes if they
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// have a user of the flag operand.
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N = NI;
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while (N->getValueType(N->getNumValues()-1) == MVT::Flag) {
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SDOperand FlagVal(N, N->getNumValues()-1);
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// There are either zero or one users of the Flag result.
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bool HasFlagUse = false;
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for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
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UI != E; ++UI)
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if (FlagVal.isOperand(*UI)) {
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HasFlagUse = true;
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NodeSUnit->FlaggedNodes.push_back(N);
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SUnitMap[N] = NodeSUnit;
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N = *UI;
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break;
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}
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if (!HasFlagUse) break;
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}
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// Now all flagged nodes are in FlaggedNodes and N is the bottom-most node.
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// Update the SUnit
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NodeSUnit->Node = N;
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SUnitMap[N] = NodeSUnit;
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// Compute the latency for the node. We use the sum of the latencies for
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// all nodes flagged together into this SUnit.
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if (InstrItins.isEmpty()) {
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// No latency information.
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NodeSUnit->Latency = 1;
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} else {
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NodeSUnit->Latency = 0;
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if (N->isTargetOpcode()) {
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unsigned SchedClass = TII->getSchedClass(N->getTargetOpcode());
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InstrStage *S = InstrItins.begin(SchedClass);
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InstrStage *E = InstrItins.end(SchedClass);
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for (; S != E; ++S)
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NodeSUnit->Latency += S->Cycles;
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}
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for (unsigned i = 0, e = NodeSUnit->FlaggedNodes.size(); i != e; ++i) {
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SDNode *FNode = NodeSUnit->FlaggedNodes[i];
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if (FNode->isTargetOpcode()) {
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unsigned SchedClass = TII->getSchedClass(FNode->getTargetOpcode());
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InstrStage *S = InstrItins.begin(SchedClass);
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InstrStage *E = InstrItins.end(SchedClass);
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for (; S != E; ++S)
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NodeSUnit->Latency += S->Cycles;
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}
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}
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}
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}
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// Pass 2: add the preds, succs, etc.
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for (unsigned su = 0, e = SUnits.size(); su != e; ++su) {
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SUnit *SU = &SUnits[su];
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SDNode *MainNode = SU->Node;
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if (MainNode->isTargetOpcode()) {
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unsigned Opc = MainNode->getTargetOpcode();
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if (TII->isTwoAddrInstr(Opc))
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SU->isTwoAddress = true;
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if (TII->isCommutableInstr(Opc))
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SU->isCommutable = true;
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}
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// Find all predecessors and successors of the group.
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// Temporarily add N to make code simpler.
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SU->FlaggedNodes.push_back(MainNode);
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for (unsigned n = 0, e = SU->FlaggedNodes.size(); n != e; ++n) {
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SDNode *N = SU->FlaggedNodes[n];
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for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
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SDNode *OpN = N->getOperand(i).Val;
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if (isPassiveNode(OpN)) continue; // Not scheduled.
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SUnit *OpSU = SUnitMap[OpN];
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assert(OpSU && "Node has no SUnit!");
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if (OpSU == SU) continue; // In the same group.
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MVT::ValueType OpVT = N->getOperand(i).getValueType();
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assert(OpVT != MVT::Flag && "Flagged nodes should be in same sunit!");
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bool isChain = OpVT == MVT::Other;
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if (SU->addPred(OpSU, isChain)) {
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if (!isChain) {
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SU->NumPreds++;
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SU->NumPredsLeft++;
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} else {
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SU->NumChainPredsLeft++;
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}
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}
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if (OpSU->addSucc(SU, isChain)) {
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if (!isChain) {
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OpSU->NumSuccs++;
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OpSU->NumSuccsLeft++;
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} else {
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OpSU->NumChainSuccsLeft++;
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}
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}
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}
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}
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// Remove MainNode from FlaggedNodes again.
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SU->FlaggedNodes.pop_back();
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}
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return;
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}
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static void CalculateDepths(SUnit &SU, unsigned Depth) {
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if (SU.Depth == 0 || Depth > SU.Depth) {
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SU.Depth = Depth;
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for (SUnit::succ_iterator I = SU.Succs.begin(), E = SU.Succs.end();
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I != E; ++I)
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CalculateDepths(*I->first, Depth+1);
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}
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}
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void ScheduleDAG::CalculateDepths() {
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SUnit *Entry = SUnitMap[DAG.getEntryNode().Val];
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::CalculateDepths(*Entry, 0U);
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for (unsigned i = 0, e = SUnits.size(); i != e; ++i)
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if (SUnits[i].Preds.size() == 0 && &SUnits[i] != Entry) {
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::CalculateDepths(SUnits[i], 0U);
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}
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}
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static void CalculateHeights(SUnit &SU, unsigned Height) {
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if (SU.Height == 0 || Height > SU.Height) {
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SU.Height = Height;
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for (SUnit::pred_iterator I = SU.Preds.begin(), E = SU.Preds.end();
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I != E; ++I)
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CalculateHeights(*I->first, Height+1);
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}
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}
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void ScheduleDAG::CalculateHeights() {
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SUnit *Root = SUnitMap[DAG.getRoot().Val];
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::CalculateHeights(*Root, 0U);
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}
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/// CountResults - The results of target nodes have register or immediate
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/// operands first, then an optional chain, and optional flag operands (which do
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/// not go into the machine instrs.)
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static unsigned CountResults(SDNode *Node) {
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unsigned N = Node->getNumValues();
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while (N && Node->getValueType(N - 1) == MVT::Flag)
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--N;
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if (N && Node->getValueType(N - 1) == MVT::Other)
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--N; // Skip over chain result.
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return N;
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}
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/// CountOperands The inputs to target nodes have any actual inputs first,
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/// followed by an optional chain operand, then flag operands. Compute the
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/// number of actual operands that will go into the machine instr.
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static unsigned CountOperands(SDNode *Node) {
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unsigned N = Node->getNumOperands();
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while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag)
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--N;
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if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
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--N; // Ignore chain if it exists.
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return N;
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}
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static const TargetRegisterClass *getInstrOperandRegClass(
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const MRegisterInfo *MRI,
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const TargetInstrInfo *TII,
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const TargetInstrDescriptor *II,
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unsigned Op) {
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if (Op >= II->numOperands) {
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assert((II->Flags & M_VARIABLE_OPS)&& "Invalid operand # of instruction");
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return NULL;
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}
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const TargetOperandInfo &toi = II->OpInfo[Op];
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return (toi.Flags & M_LOOK_UP_PTR_REG_CLASS)
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? TII->getPointerRegClass() : MRI->getRegClass(toi.RegClass);
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}
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static unsigned CreateVirtualRegisters(const MRegisterInfo *MRI,
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MachineInstr *MI,
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unsigned NumResults,
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SSARegMap *RegMap,
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const TargetInstrInfo *TII,
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const TargetInstrDescriptor &II) {
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// Create the result registers for this node and add the result regs to
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// the machine instruction.
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unsigned ResultReg =
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RegMap->createVirtualRegister(getInstrOperandRegClass(MRI, TII, &II, 0));
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MI->addRegOperand(ResultReg, true);
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for (unsigned i = 1; i != NumResults; ++i) {
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const TargetRegisterClass *RC = getInstrOperandRegClass(MRI, TII, &II, i);
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assert(RC && "Isn't a register operand!");
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MI->addRegOperand(RegMap->createVirtualRegister(RC), true);
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}
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return ResultReg;
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}
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/// getVR - Return the virtual register corresponding to the specified result
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/// of the specified node.
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static unsigned getVR(SDOperand Op, std::map<SDNode*, unsigned> &VRBaseMap) {
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std::map<SDNode*, unsigned>::iterator I = VRBaseMap.find(Op.Val);
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assert(I != VRBaseMap.end() && "Node emitted out of order - late");
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return I->second + Op.ResNo;
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}
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/// AddOperand - Add the specified operand to the specified machine instr. II
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/// specifies the instruction information for the node, and IIOpNum is the
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/// operand number (in the II) that we are adding. IIOpNum and II are used for
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/// assertions only.
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void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
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unsigned IIOpNum,
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const TargetInstrDescriptor *II,
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std::map<SDNode*, unsigned> &VRBaseMap) {
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if (Op.isTargetOpcode()) {
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// Note that this case is redundant with the final else block, but we
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// include it because it is the most common and it makes the logic
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// simpler here.
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assert(Op.getValueType() != MVT::Other &&
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Op.getValueType() != MVT::Flag &&
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"Chain and flag operands should occur at end of operand list!");
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// Get/emit the operand.
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unsigned VReg = getVR(Op, VRBaseMap);
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MI->addRegOperand(VReg, false);
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// Verify that it is right.
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assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
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if (II) {
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const TargetRegisterClass *RC =
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getInstrOperandRegClass(MRI, TII, II, IIOpNum);
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assert(RC && "Don't have operand info for this instruction!");
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assert(RegMap->getRegClass(VReg) == RC &&
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"Register class of operand and regclass of use don't agree!");
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}
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} else if (ConstantSDNode *C =
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dyn_cast<ConstantSDNode>(Op)) {
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MI->addImmOperand(C->getValue());
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} else if (RegisterSDNode*R =
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dyn_cast<RegisterSDNode>(Op)) {
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MI->addRegOperand(R->getReg(), false);
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} else if (GlobalAddressSDNode *TGA =
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dyn_cast<GlobalAddressSDNode>(Op)) {
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MI->addGlobalAddressOperand(TGA->getGlobal(), TGA->getOffset());
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} else if (BasicBlockSDNode *BB =
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dyn_cast<BasicBlockSDNode>(Op)) {
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MI->addMachineBasicBlockOperand(BB->getBasicBlock());
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} else if (FrameIndexSDNode *FI =
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dyn_cast<FrameIndexSDNode>(Op)) {
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MI->addFrameIndexOperand(FI->getIndex());
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} else if (JumpTableSDNode *JT =
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dyn_cast<JumpTableSDNode>(Op)) {
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MI->addJumpTableIndexOperand(JT->getIndex());
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} else if (ConstantPoolSDNode *CP =
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dyn_cast<ConstantPoolSDNode>(Op)) {
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int Offset = CP->getOffset();
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unsigned Align = CP->getAlignment();
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const Type *Type = CP->getType();
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// MachineConstantPool wants an explicit alignment.
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if (Align == 0) {
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if (Type == Type::DoubleTy)
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Align = 3; // always 8-byte align doubles.
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else {
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Align = TM.getTargetData()->getTypeAlignmentShift(Type);
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if (Align == 0) {
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// Alignment of packed types. FIXME!
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Align = TM.getTargetData()->getTypeSize(Type);
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Align = Log2_64(Align);
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}
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}
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}
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unsigned Idx;
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if (CP->isMachineConstantPoolEntry())
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Idx = ConstPool->getConstantPoolIndex(CP->getMachineCPVal(), Align);
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else
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Idx = ConstPool->getConstantPoolIndex(CP->getConstVal(), Align);
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MI->addConstantPoolIndexOperand(Idx, Offset);
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} else if (ExternalSymbolSDNode *ES =
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dyn_cast<ExternalSymbolSDNode>(Op)) {
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MI->addExternalSymbolOperand(ES->getSymbol());
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} else {
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assert(Op.getValueType() != MVT::Other &&
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Op.getValueType() != MVT::Flag &&
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"Chain and flag operands should occur at end of operand list!");
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unsigned VReg = getVR(Op, VRBaseMap);
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MI->addRegOperand(VReg, false);
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// Verify that it is right.
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assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
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if (II) {
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const TargetRegisterClass *RC =
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getInstrOperandRegClass(MRI, TII, II, IIOpNum);
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assert(RC && "Don't have operand info for this instruction!");
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assert(RegMap->getRegClass(VReg) == RC &&
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"Register class of operand and regclass of use don't agree!");
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}
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}
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}
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/// EmitNode - Generate machine code for an node and needed dependencies.
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///
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void ScheduleDAG::EmitNode(SDNode *Node,
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std::map<SDNode*, unsigned> &VRBaseMap) {
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unsigned VRBase = 0; // First virtual register for node
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// If machine instruction
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if (Node->isTargetOpcode()) {
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unsigned Opc = Node->getTargetOpcode();
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const TargetInstrDescriptor &II = TII->get(Opc);
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unsigned NumResults = CountResults(Node);
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unsigned NodeOperands = CountOperands(Node);
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unsigned NumMIOperands = NodeOperands + NumResults;
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#ifndef NDEBUG
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assert((unsigned(II.numOperands) == NumMIOperands ||
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(II.Flags & M_VARIABLE_OPS)) &&
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"#operands for dag node doesn't match .td file!");
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#endif
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// Create the new machine instruction.
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MachineInstr *MI = new MachineInstr(Opc, NumMIOperands);
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// Add result register values for things that are defined by this
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// instruction.
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// If the node is only used by a CopyToReg and the dest reg is a vreg, use
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// the CopyToReg'd destination register instead of creating a new vreg.
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if (NumResults == 1) {
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for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
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UI != E; ++UI) {
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SDNode *Use = *UI;
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if (Use->getOpcode() == ISD::CopyToReg &&
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Use->getOperand(2).Val == Node) {
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unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
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if (MRegisterInfo::isVirtualRegister(Reg)) {
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VRBase = Reg;
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MI->addRegOperand(Reg, true);
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break;
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}
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}
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}
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}
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// Otherwise, create new virtual registers.
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if (NumResults && VRBase == 0)
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VRBase = CreateVirtualRegisters(MRI, MI, NumResults, RegMap, TII, II);
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// Emit all of the actual operands of this instruction, adding them to the
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// instruction as appropriate.
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for (unsigned i = 0; i != NodeOperands; ++i)
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AddOperand(MI, Node->getOperand(i), i+NumResults, &II, VRBaseMap);
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// Commute node if it has been determined to be profitable.
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if (CommuteSet.count(Node)) {
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MachineInstr *NewMI = TII->commuteInstruction(MI);
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if (NewMI == 0)
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DEBUG(std::cerr << "Sched: COMMUTING FAILED!\n");
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else {
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DEBUG(std::cerr << "Sched: COMMUTED TO: " << *NewMI);
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if (MI != NewMI) {
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delete MI;
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MI = NewMI;
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}
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}
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}
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// Now that we have emitted all operands, emit this instruction itself.
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if ((II.Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION) == 0) {
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BB->insert(BB->end(), MI);
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} else {
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// Insert this instruction into the end of the basic block, potentially
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// taking some custom action.
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BB = DAG.getTargetLoweringInfo().InsertAtEndOfBasicBlock(MI, BB);
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}
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} else {
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switch (Node->getOpcode()) {
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default:
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#ifndef NDEBUG
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Node->dump();
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#endif
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assert(0 && "This target-independent node should have been selected!");
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case ISD::EntryToken: // fall thru
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case ISD::TokenFactor:
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break;
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case ISD::CopyToReg: {
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unsigned InReg = getVR(Node->getOperand(2), VRBaseMap);
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unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
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if (InReg != DestReg) // Coalesced away the copy?
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|
MRI->copyRegToReg(*BB, BB->end(), DestReg, InReg,
|
|
RegMap->getRegClass(InReg));
|
|
break;
|
|
}
|
|
case ISD::CopyFromReg: {
|
|
unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
|
|
if (MRegisterInfo::isVirtualRegister(SrcReg)) {
|
|
VRBase = SrcReg; // Just use the input register directly!
|
|
break;
|
|
}
|
|
|
|
// If the node is only used by a CopyToReg and the dest reg is a vreg, use
|
|
// the CopyToReg'd destination register instead of creating a new vreg.
|
|
for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
|
|
UI != E; ++UI) {
|
|
SDNode *Use = *UI;
|
|
if (Use->getOpcode() == ISD::CopyToReg &&
|
|
Use->getOperand(2).Val == Node) {
|
|
unsigned DestReg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
|
|
if (MRegisterInfo::isVirtualRegister(DestReg)) {
|
|
VRBase = DestReg;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
// Figure out the register class to create for the destreg.
|
|
const TargetRegisterClass *TRC = 0;
|
|
if (VRBase) {
|
|
TRC = RegMap->getRegClass(VRBase);
|
|
} else {
|
|
|
|
// Pick the register class of the right type that contains this physreg.
|
|
for (MRegisterInfo::regclass_iterator I = MRI->regclass_begin(),
|
|
E = MRI->regclass_end(); I != E; ++I)
|
|
if ((*I)->hasType(Node->getValueType(0)) &&
|
|
(*I)->contains(SrcReg)) {
|
|
TRC = *I;
|
|
break;
|
|
}
|
|
assert(TRC && "Couldn't find register class for reg copy!");
|
|
|
|
// Create the reg, emit the copy.
|
|
VRBase = RegMap->createVirtualRegister(TRC);
|
|
}
|
|
MRI->copyRegToReg(*BB, BB->end(), VRBase, SrcReg, TRC);
|
|
break;
|
|
}
|
|
case ISD::INLINEASM: {
|
|
unsigned NumOps = Node->getNumOperands();
|
|
if (Node->getOperand(NumOps-1).getValueType() == MVT::Flag)
|
|
--NumOps; // Ignore the flag operand.
|
|
|
|
// Create the inline asm machine instruction.
|
|
MachineInstr *MI =
|
|
new MachineInstr(BB, TargetInstrInfo::INLINEASM, (NumOps-2)/2+1);
|
|
|
|
// Add the asm string as an external symbol operand.
|
|
const char *AsmStr =
|
|
cast<ExternalSymbolSDNode>(Node->getOperand(1))->getSymbol();
|
|
MI->addExternalSymbolOperand(AsmStr);
|
|
|
|
// Add all of the operand registers to the instruction.
|
|
for (unsigned i = 2; i != NumOps;) {
|
|
unsigned Flags = cast<ConstantSDNode>(Node->getOperand(i))->getValue();
|
|
unsigned NumVals = Flags >> 3;
|
|
|
|
MI->addImmOperand(Flags);
|
|
++i; // Skip the ID value.
|
|
|
|
switch (Flags & 7) {
|
|
default: assert(0 && "Bad flags!");
|
|
case 1: // Use of register.
|
|
for (; NumVals; --NumVals, ++i) {
|
|
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
|
|
MI->addRegOperand(Reg, false);
|
|
}
|
|
break;
|
|
case 2: // Def of register.
|
|
for (; NumVals; --NumVals, ++i) {
|
|
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
|
|
MI->addRegOperand(Reg, true);
|
|
}
|
|
break;
|
|
case 3: { // Immediate.
|
|
assert(NumVals == 1 && "Unknown immediate value!");
|
|
uint64_t Val = cast<ConstantSDNode>(Node->getOperand(i))->getValue();
|
|
MI->addImmOperand(Val);
|
|
++i;
|
|
break;
|
|
}
|
|
case 4: // Addressing mode.
|
|
// The addressing mode has been selected, just add all of the
|
|
// operands to the machine instruction.
|
|
for (; NumVals; --NumVals, ++i)
|
|
AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap);
|
|
break;
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
assert(!VRBaseMap.count(Node) && "Node emitted out of order - early");
|
|
VRBaseMap[Node] = VRBase;
|
|
}
|
|
|
|
void ScheduleDAG::EmitNoop() {
|
|
TII->insertNoop(*BB, BB->end());
|
|
}
|
|
|
|
/// EmitSchedule - Emit the machine code in scheduled order.
|
|
void ScheduleDAG::EmitSchedule() {
|
|
// If this is the first basic block in the function, and if it has live ins
|
|
// that need to be copied into vregs, emit the copies into the top of the
|
|
// block before emitting the code for the block.
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
if (&MF.front() == BB && MF.livein_begin() != MF.livein_end()) {
|
|
for (MachineFunction::livein_iterator LI = MF.livein_begin(),
|
|
E = MF.livein_end(); LI != E; ++LI)
|
|
if (LI->second)
|
|
MRI->copyRegToReg(*MF.begin(), MF.begin()->end(), LI->second,
|
|
LI->first, RegMap->getRegClass(LI->second));
|
|
}
|
|
|
|
|
|
// Finally, emit the code for all of the scheduled instructions.
|
|
std::map<SDNode*, unsigned> VRBaseMap;
|
|
for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
|
|
if (SUnit *SU = Sequence[i]) {
|
|
for (unsigned j = 0, ee = SU->FlaggedNodes.size(); j != ee; j++)
|
|
EmitNode(SU->FlaggedNodes[j], VRBaseMap);
|
|
EmitNode(SU->Node, VRBaseMap);
|
|
} else {
|
|
// Null SUnit* is a noop.
|
|
EmitNoop();
|
|
}
|
|
}
|
|
}
|
|
|
|
/// dump - dump the schedule.
|
|
void ScheduleDAG::dumpSchedule() const {
|
|
for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
|
|
if (SUnit *SU = Sequence[i])
|
|
SU->dump(&DAG);
|
|
else
|
|
std::cerr << "**** NOOP ****\n";
|
|
}
|
|
}
|
|
|
|
|
|
/// Run - perform scheduling.
|
|
///
|
|
MachineBasicBlock *ScheduleDAG::Run() {
|
|
TII = TM.getInstrInfo();
|
|
MRI = TM.getRegisterInfo();
|
|
RegMap = BB->getParent()->getSSARegMap();
|
|
ConstPool = BB->getParent()->getConstantPool();
|
|
|
|
Schedule();
|
|
return BB;
|
|
}
|
|
|
|
/// SUnit - Scheduling unit. It's an wrapper around either a single SDNode or
|
|
/// a group of nodes flagged together.
|
|
void SUnit::dump(const SelectionDAG *G) const {
|
|
std::cerr << "SU(" << NodeNum << "): ";
|
|
Node->dump(G);
|
|
std::cerr << "\n";
|
|
if (FlaggedNodes.size() != 0) {
|
|
for (unsigned i = 0, e = FlaggedNodes.size(); i != e; i++) {
|
|
std::cerr << " ";
|
|
FlaggedNodes[i]->dump(G);
|
|
std::cerr << "\n";
|
|
}
|
|
}
|
|
}
|
|
|
|
void SUnit::dumpAll(const SelectionDAG *G) const {
|
|
dump(G);
|
|
|
|
std::cerr << " # preds left : " << NumPredsLeft << "\n";
|
|
std::cerr << " # succs left : " << NumSuccsLeft << "\n";
|
|
std::cerr << " # chain preds left : " << NumChainPredsLeft << "\n";
|
|
std::cerr << " # chain succs left : " << NumChainSuccsLeft << "\n";
|
|
std::cerr << " Latency : " << Latency << "\n";
|
|
std::cerr << " Depth : " << Depth << "\n";
|
|
std::cerr << " Height : " << Height << "\n";
|
|
|
|
if (Preds.size() != 0) {
|
|
std::cerr << " Predecessors:\n";
|
|
for (SUnit::const_succ_iterator I = Preds.begin(), E = Preds.end();
|
|
I != E; ++I) {
|
|
if (I->second)
|
|
std::cerr << " ch #";
|
|
else
|
|
std::cerr << " val #";
|
|
std::cerr << I->first << "\n";
|
|
}
|
|
}
|
|
if (Succs.size() != 0) {
|
|
std::cerr << " Successors:\n";
|
|
for (SUnit::const_succ_iterator I = Succs.begin(), E = Succs.end();
|
|
I != E; ++I) {
|
|
if (I->second)
|
|
std::cerr << " ch #";
|
|
else
|
|
std::cerr << " val #";
|
|
std::cerr << I->first << "\n";
|
|
}
|
|
}
|
|
std::cerr << "\n";
|
|
}
|