Oliver Stannard 9bb3f37aa4 [AArch64] Fix fast-isel of cbz of i1, i8, i16 ...

This fixes a miscompilation in the AArch64 fast-isel which was
triggered when a branch is based on an icmp with condition eq or ne,
and type i1, i8 or i16. The cbz instruction compares the whole 32-bit
register, so values with the bottom 1, 8 or 16 bits clear would cause
the wrong branch to be taken.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220553 91177308-0d34-0410-b5e6-96231b3b80d8

2014-10-24 09:54:41 +00:00

..

AsmParser

[AArch64] Add support for the .inst directive.

2014-10-22 20:35:57 +00:00

Disassembler

[AArch64] Allow access to all system registers with MRS/MSR instructions.

2014-10-01 10:13:59 +00:00

InstPrinter

[AArch64] Allow access to all system registers with MRS/MSR instructions.

2014-10-01 10:13:59 +00:00

MCTargetDesc

[AArch64] Add support for the .inst directive.

2014-10-22 20:35:57 +00:00

TargetInfo

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Utils

[AArch64] Allow access to all system registers with MRS/MSR instructions.

2014-10-01 10:13:59 +00:00

AArch64.h

[AArch64] Add workaround for Cortex-A53 erratum (835769)

2014-10-13 10:12:35 +00:00

AArch64.td

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AArch64A53Fix835769.cpp

[AArch64] Fix crash with empty/pseudo-only blocks in A53 erratum (835769) workaround

2014-10-14 14:02:41 +00:00

AArch64A57FPLoadBalancing.cpp

Eliminate some deep std::vector copies. NFC.

2014-10-03 18:33:16 +00:00

AArch64AddressTypePromotion.cpp

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AArch64AdvSIMDScalarPass.cpp

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AArch64AsmPrinter.cpp

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AArch64BranchRelaxation.cpp

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AArch64CallingConvention.td

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AArch64CleanupLocalDynamicTLSPass.cpp

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AArch64CollectLOH.cpp

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AArch64ConditionalCompares.cpp

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AArch64ConditionOptimizer.cpp

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AArch64DeadRegisterDefinitionsPass.cpp

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AArch64ExpandPseudoInsts.cpp

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AArch64FastISel.cpp

[AArch64] Fix fast-isel of cbz of i1, i8, i16

2014-10-24 09:54:41 +00:00

AArch64FrameLowering.cpp

[Stackmaps] Make ithe frame-pointer required for stackmaps.

2014-10-02 22:21:49 +00:00

AArch64FrameLowering.h

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AArch64InstrAtomics.td

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AArch64InstrFormats.td

[AArch64] Allow access to all system registers with MRS/MSR instructions.

2014-10-01 10:13:59 +00:00

AArch64InstrInfo.cpp

Remove unused variable.

2014-10-15 00:09:07 +00:00

AArch64InstrInfo.h

[AAarch64] Optimize CSINC-branch sequence

2014-10-14 23:07:53 +00:00

AArch64InstrInfo.td

[AArch64] Generate vector signed/unsigned mul and mla/mls long.

2014-10-08 02:31:24 +00:00

AArch64ISelDAGToDAG.cpp

[AArch64]Select wide immediate offset into [Base+XReg] addressing mode

2014-10-14 06:50:36 +00:00

AArch64ISelLowering.cpp

[AArch64] Fix a silent codegen fault in BUILD_VECTOR lowering.

2014-10-17 17:06:31 +00:00

AArch64ISelLowering.h

[AArch64] Generate vector signed/unsigned mul and mla/mls long.

2014-10-08 02:31:24 +00:00

AArch64LoadStoreOptimizer.cpp

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AArch64MachineCombinerPattern.h

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AArch64MachineFunctionInfo.h

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AArch64MCInstLower.cpp

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AArch64MCInstLower.h

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AArch64PBQPRegAlloc.cpp

[AArch64] Cleanup A57PBQPConstraints

2014-10-22 12:40:20 +00:00

AArch64PBQPRegAlloc.h

[AArch64] Cleanup A57PBQPConstraints

2014-10-22 12:40:20 +00:00

AArch64PerfectShuffle.h

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AArch64PromoteConstant.cpp

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AArch64RegisterInfo.cpp

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AArch64RegisterInfo.h

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AArch64RegisterInfo.td

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AArch64SchedA53.td

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AArch64SchedA57.td

[AArch64] Enable partial & runtime unrolling on cortex-a57.

2014-10-09 10:13:27 +00:00

AArch64SchedA57WriteRes.td

[AArch64] Refines the Cortex-A57 Machine Model

2014-09-29 21:27:36 +00:00

AArch64SchedCyclone.td

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AArch64Schedule.td

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AArch64SelectionDAGInfo.cpp

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AArch64SelectionDAGInfo.h

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AArch64StorePairSuppress.cpp

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AArch64Subtarget.cpp

[AArch64] Cleanup A57PBQPConstraints

2014-10-22 12:40:20 +00:00

AArch64Subtarget.h

[PBQP] Replace PBQPBuilder with composable constraints (PBQPRAConstraint).

2014-10-09 18:20:51 +00:00

AArch64TargetMachine.cpp

[PBQP] Teach PassConfig to tell if the default register allocator is used.

2014-10-21 20:47:22 +00:00

AArch64TargetMachine.h

[PBQP] Teach PassConfig to tell if the default register allocator is used.

2014-10-21 20:47:22 +00:00

AArch64TargetObjectFile.cpp

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AArch64TargetObjectFile.h

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AArch64TargetTransformInfo.cpp

[AArch64] Enable partial & runtime unrolling on cortex-a57.

2014-10-09 10:13:27 +00:00

CMakeLists.txt

[AArch64] Add workaround for Cortex-A53 erratum (835769)

2014-10-13 10:12:35 +00:00

LLVMBuild.txt

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Makefile

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