llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-17 06:33:21 +00:00

History

Quentin Colombet c34693f6ef [DAGCombiner] Slice a big load in two loads when the element are next to each

other in memory and the target has paired load and performs post-isel loads
combining.

E.g., this optimization will transform something like this:
 a = load i64* addr
 b = trunc i64 a to i32
 c = lshr i64 a, 32
 d = trunc i64 c to i32

into:
 b = load i32* addr1
 d = load i32* addr2
Where addr1 = addr2 +/- sizeof(i32), if the target supports paired load and
performs post-isel loads combining.

One should overload TargetLowering::hasPairedLoad to provide this information.
The default is false.

<rdar://problem/14477220>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192471 91177308-0d34-0410-b5e6-96231b3b80d8

2013-10-11 18:01:14 +00:00

Analysis

Rename DataLayout variables TD -> DL

2013-10-03 19:50:01 +00:00

AsmParser

Add a GlobalAlias::isValidLinkage to reduce code duplication.

2013-10-09 16:07:32 +00:00

Bitcode

AutoUpgrade: upgrade from scalar TBAA format to struct-path aware TBAA format.

2013-09-28 00:22:27 +00:00

CodeGen

[DAGCombiner] Slice a big load in two loads when the element are next to each