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llvm-6502/test/CodeGen/AArch64
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Chad Rosier c3de5ed072 [AArch64] Implement the isZExtFree APIs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205926 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 20:51:21 +00:00
..
128bit_load_store.ll
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adc.ll
AArch64_BE function argument passing for ARM ABI
2014-03-26 14:51:22 +00:00
addsub_ext.ll
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addsub-shifted.ll
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addsub.ll
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alloca.ll
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analyze-branch.ll
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assertion-rc-mismatch.ll
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atomic-ops-not-barriers.ll
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atomic-ops.ll
IR: add a second ordering operand to cmpxhg for failure
2014-03-11 10:48:52 +00:00
basic-pic.ll
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bitfield-insert-0.ll
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bitfield-insert.ll
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bitfield.ll
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blockaddress.ll
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bool-loads.ll
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breg.ll
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callee-save.ll
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code-model-large-abs.ll
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compare-branch.ll
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complex-copy-noneon.ll
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concatvector-bugs.ll
AArch64: fix LowerCONCAT_VECTORS for new CodeGen.
2014-03-10 09:34:07 +00:00
cond-sel.ll
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cpus.ll
llvm/test/CodeGen/AArch64/cpus.ll: Tweak to use -mtriple=aarch64-unknown-unknown, or this would crash for targeting pecoff like *-mingw32.
2014-02-13 11:06:23 +00:00
directcond.ll
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dp1.ll
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dp2.ll
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dp-3source.ll
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eliminate-trunc.ll
[AArch64] Implement the isTruncateFree API.
2014-04-09 20:43:40 +00:00
extern-weak.ll
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extract.ll
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fastcc-reserved.ll
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fastcc.ll
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fcmp.ll
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fcvt-fixed.ll
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fcvt-int.ll
Fix broken CHECK lines
2014-02-16 07:31:05 +00:00
flags-multiuse.ll
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floatdp_1source.ll
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floatdp_2source.ll
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fp128-folding.ll
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fp128.ll
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fp-cond-sel.ll
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fp-dp3.ll
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fpimm.ll
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frameaddr.ll
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free-zext.ll
[AArch64] Implement the isZExtFree APIs.
2014-04-09 20:51:21 +00:00
func-argpassing.ll
AArch64_BE function argument passing for ARM ABI
2014-03-26 14:51:22 +00:00
func-calls.ll
AArch64_BE function argument passing for ARM ABI
2014-03-26 14:51:22 +00:00
global-alignment.ll
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got-abuse.ll
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i128-align.ll
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i128-shift.ll
[AArch64] Lower SHL_PARTS, SRA_PARTS and SRL_PARTS
2014-03-27 16:28:09 +00:00
illegal-float-ops.ll
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init-array.ll
Make sure -use-init-array has intended effect on all AArch64 ELF targets, not just linux.
2014-01-10 13:41:49 +00:00
inline-asm-constraints-badI.ll
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inline-asm-constraints-badK2.ll
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inline-asm-constraints-badK.ll
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inline-asm-constraints-badL.ll
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inline-asm-constraints.ll
Re-commit: Demote EmitRawText call in AsmPrinter::EmitInlineAsm() and remove hasRawTextSupport() call
2014-02-13 14:44:26 +00:00
inline-asm-modifiers.ll
Re-commit: Demote EmitRawText call in AsmPrinter::EmitInlineAsm() and remove hasRawTextSupport() call
2014-02-13 14:44:26 +00:00
jump-table.ll
[AArch64] Remove .data_region directive from AArch64.
2014-03-21 02:12:48 +00:00
large-consts.ll
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large-frame.ll
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ldst-regoffset.ll
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ldst-unscaledimm.ll
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ldst-unsignedimm.ll
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lit.local.cfg
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literal_pools.ll
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local_vars.ll
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logical_shifted_reg.ll
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logical-imm.ll
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mature-mc-support.ll
Specify a triple. MachO AArch64 support is missing.
2014-02-13 15:30:06 +00:00
misched-basic-A53.ll
[AArch64] Add SchedRW lists to NEON instructions.
2014-03-21 19:34:41 +00:00
movw-consts.ll
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movw-shift-encoding.ll
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mul-lohi.ll
AArch64_BE function argument passing for ARM ABI
2014-03-26 14:51:22 +00:00
neon-2velem-high.ll
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neon-2velem.ll
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neon-3vdiff.ll
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neon-aba-abd.ll
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neon-across.ll
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neon-add-pairwise.ll
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neon-add-sub.ll
[AArch64]Fix the problems that can't select mul/add/sub of v1i8/v1i16/v1i32 types.
2014-02-13 05:42:33 +00:00
neon-bitcast.ll
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neon-bitwise-instructions.ll
Teach the DAGCombiner how to fold 'vselect' dag nodes according
2014-01-08 18:33:04 +00:00
neon-bsl.ll
[AArch64] Added vselect patterns with float and double types
2014-01-23 19:18:57 +00:00
neon-compare-instructions.ll
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neon-copy.ll
[AArch64]Implement the copy of two FPR8 registers by using FMOVss of two FPR32 registers in copyPhysReg.
2014-02-10 03:16:22 +00:00
neon-copyPhysReg-tuple.ll
[AArch64]Add support to copy D tuples such as DPair/DTriple/DQuad and Q tuples such as QPair/QTriple/QQuad. There is no test case for D tuple as the original test cases are too large. As the copy of the D tuple is similar to the Q tuple, the correctness can be guaranteed.
2014-01-07 10:00:03 +00:00
neon-crypto.ll
AArch64 & ARM: refactor crypto intrinsics to take scalars
2014-02-03 17:27:49 +00:00
neon-diagnostics.ll
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neon-extract.ll
[AArch64 NEON] Fix a bug caused by undef lane when generating VEXT.
2014-01-21 01:48:52 +00:00
neon-facge-facgt.ll
ARM & AArch64: merge NEON absolute compare intrinsics
2014-02-04 14:55:42 +00:00
neon-fma.ll
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neon-fpround_f128.ll
[AArch64 NEON] Add test case for vector FP_ROUND.
2014-01-26 02:23:33 +00:00
neon-frsqrt-frecp.ll
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neon-halving-add-sub.ll
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neon-load-store-v1i32.ll
[AArch64]Fix the problem can't select f16_to_f32 and f32_to_f16.
2014-01-17 06:23:30 +00:00
neon-max-min-pairwise.ll
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neon-max-min.ll
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neon-misc-scalar.ll
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neon-misc.ll
[AArch64 NEON] Custom lower conversion between vector integer and vector floating point if element bit-width doesn't match.
2014-01-17 05:52:35 +00:00
neon-mla-mls.ll
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neon-mov.ll
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neon-mul-div.ll
[AArch64]Fix the problems that can't select mul/add/sub of v1i8/v1i16/v1i32 types.
2014-02-13 05:42:33 +00:00
neon-or-combine.ll
[AArch64] Fix assertion failure caused by an invalid comparison between APInt values.
2014-01-13 16:51:00 +00:00
neon-perm.ll
[AArch64 NEON] Add more scenarios to use perm instructions when lowering shuffle_vector
2014-01-13 01:56:29 +00:00
neon-rounding-halving-add.ll
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neon-rounding-shift.ll
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neon-saturating-add-sub.ll
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neon-saturating-rounding-shift.ll
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neon-saturating-shift.ll
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neon-scalar-abs.ll
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neon-scalar-add-sub.ll
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neon-scalar-by-elem-fma.ll
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neon-scalar-by-elem-mul.ll
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neon-scalar-compare.ll
ARM & AArch64: merge NEON absolute compare intrinsics
2014-02-04 14:55:42 +00:00
neon-scalar-copy.ll
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neon-scalar-cvt.ll
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neon-scalar-ext.ll
Improve pattern match from v1i8 to v1i32 for AArch64 Neon.
2014-01-26 04:55:53 +00:00
neon-scalar-extract-narrow.ll
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neon-scalar-fabd.ll
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neon-scalar-fcvt.ll
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neon-scalar-fp-compare.ll
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neon-scalar-mul.ll
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neon-scalar-neg.ll
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neon-scalar-recip.ll
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neon-scalar-reduce-pairwise.ll
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neon-scalar-rounding-shift.ll
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neon-scalar-saturating-add-sub.ll
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neon-scalar-saturating-rounding-shift.ll
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neon-scalar-saturating-shift.ll
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neon-scalar-shift-imm.ll
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neon-scalar-shift.ll
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neon-select_cc.ll
[AArch64 NEON] Fix a bug to avoid using floating type as condition type in lowering SELECT_CC.
2014-02-14 09:41:15 +00:00
neon-shift-left-long.ll
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neon-shift.ll
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neon-shl-ashr-lshr.ll
Make DAGCombiner work on vector bitshifts with constant splat vectors.
2014-03-17 18:58:01 +00:00
neon-simd-ldst-multi-elem.ll
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neon-simd-ldst-one.ll
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neon-simd-ldst.ll
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neon-simd-post-ldst-multi-elem.ll
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neon-simd-post-ldst-one.ll
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neon-simd-shift.ll
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neon-simd-tbl.ll
AArch64: simplify tbl/tbx polymorphism
2014-02-26 11:55:09 +00:00
neon-simd-vget.ll
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neon-spill-fpr8-fpr16.ll
[AArch64]Add support for spilling FPR8/FPR16.
2014-02-13 02:36:58 +00:00
neon-truncStore-extLoad.ll
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neon-v1i1-setcc.ll
[AArch64]Fix the assertion failure caused by "v1i1 SETCC" DAG node.
2014-02-14 02:21:56 +00:00
neon-vector-list-spill.ll
[AArch64]Add support to spill/fill D tuples such as DPair/DTriple/DQuad. There is no test cases for D tuple as the original test cases are too large. As the spill/fill of the D tuple is similar to the Q tuple, the correctness can be guaranteed.
2014-01-07 10:50:43 +00:00
pic-eh-stubs.ll
AArch64_BE Elf support for MC-JIT runtime dynamic linker
2014-03-26 14:57:32 +00:00
ragreedy-csr.ll
Register Allocator: check other options before using a CSR for the first time.
2014-03-25 00:16:25 +00:00
regress-bitcast-formals.ll
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regress-f128csel-flags.ll
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regress-fp128-livein.ll
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regress-tail-livereg.ll
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regress-tblgen-chains.ll
[AArch64] Implement the isZExtFree APIs.
2014-04-09 20:51:21 +00:00
regress-w29-reserved-with-fp.ll
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regress-wzr-allocatable.ll
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returnaddr.ll
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setcc-takes-i32.ll
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sext_inreg.ll
For AArch64, lowering sext_inreg and generate optimized code by using SXTL.
2014-01-15 05:08:01 +00:00
sibling-call.ll
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sincos-expansion.ll
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sincospow-vector-expansion.ll
[AArch64] Expanded sin, cos, pow with FP vector types inputs
2014-02-18 20:31:05 +00:00
tail-call.ll
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tls-dynamic-together.ll
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tls-dynamics.ll
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tls-execs.ll
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tst-br.ll
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variadic.ll
AArch64: __va_list.__stack must be 8-byte aligned
2014-02-20 17:19:26 +00:00
zero-reg.ll
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