llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-25 00:33:15 +00:00

History

Evan Cheng c4b527ac06 DAGCombine's logic for forming pre- and post- indexed loads / stores were being

overly conservative. It was concerned about cases where it would prohibit
folding simple [r, c] addressing modes. e.g.
  ldr r0, [r2]
  ldr r1, [r2, #4]
=>
  ldr r0, [r2], #4
  ldr r1, [r2]
Change the logic to look for such cases which allows it to form indexed memory
ops more aggressively.

rdar://10674430


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148086 91177308-0d34-0410-b5e6-96231b3b80d8

2012-01-13 01:37:24 +00:00

ARM

DAGCombine's logic for forming pre- and post- indexed loads / stores were being

2012-01-13 01:37:24 +00:00

CBackend

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CellSPU

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CPP

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Generic

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