6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-29 10:32:47 +00:00
Code Issues Projects Releases Wiki Activity
c56226c6d1
llvm-6502/test/MC
History
Davide Italiano 8667ab752e [MC][Target] Implement support for R_X86_64_SIZE{32,64}. 
Differential Revision:	D7990
Reviewed by:	rafael, majnemer


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231216 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-04 06:49:39 +00:00
..
AArch64 [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
ARM DebugInfo: Move new hierarchy into place 2015-03-03 17:24:31 +00:00
AsmParser MC: Don't emit .no_dead_strip on targets which don't support it 2014-12-24 04:11:42 +00:00
COFF [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
Disassembler Add the following 64-bit vector integer arithmetic instructions added in POWER8: 2015-03-03 19:55:45 +00:00
ELF [MC][Target] Implement support for R_X86_64_SIZE{32,64}. 2015-03-04 06:49:39 +00:00
Hexagon [Hexagon] Updating predicate register transfers and adding tstbit to allow select selection. Updating ll tests with predicate transfers that previously had nop encodings. 2014-12-09 18:16:49 +00:00
MachO [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
Markup
Mips [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
PowerPC Add the following 64-bit vector integer arithmetic instructions added in POWER8: 2015-03-03 19:55:45 +00:00
R600 R600/SI: Add a stub GCNTargetMachine 2015-01-06 18:00:21 +00:00
Sparc
SystemZ [SystemZ] Support all TLS access models - MC part 2015-02-18 09:11:36 +00:00
X86 DebugInfo: Move new hierarchy into place 2015-03-03 17:24:31 +00:00