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7cb1b5f5bf
llc using the host cpu features and *waning* on unknown features is probably not a good thing :-( git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189144 91177308-0d34-0410-b5e6-96231b3b80d8
20 lines
933 B
LLVM
20 lines
933 B
LLVM
; RUN: llc -march=x86-64 -mattr=+sse4.1 -mcpu=penryn < %s | FileCheck %s -check-prefix=CHECK-W-SSE4
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; RUN: llc -march=x86-64 -mattr=-sse4.1 -mcpu=penryn < %s | FileCheck %s -check-prefix=CHECK-WO-SSE4
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; Test case for r146671
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
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target triple = "x86_64-apple-macosx10.7"
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define <16 x i8> @shift(<16 x i8> %a, <16 x i8> %b) nounwind {
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; Make sure operands to pblend are in the right order.
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; CHECK-W-SSE4: psllw $4, [[REG1:%xmm.]]
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; CHECK-W-SSE4: pblendvb [[REG1]],{{ %xmm.}}
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; CHECK-W-SSE4: psllw $2
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; Make sure we're masking and pcmp'ing the VSELECT conditon vector.
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; CHECK-WO-SSE4: psllw $5, [[REG1:%xmm.]]
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; CHECK-WO-SSE4: pand [[REG1]], [[REG2:%xmm.]]
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; CHECK-WO-SSE4: pcmpeqb {{%xmm., }}[[REG2]]
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%1 = shl <16 x i8> %a, %b
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ret <16 x i8> %1
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}
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