Johnny Chen c584e317e9 ARM disassembler was erroneously accepting an invalid LSL instruction. ... For register-controlled shifts, we should check that the encoding constraint Inst{7} = 0 and Inst{4} = 1 is satisfied. rdar://problem/9237693 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128941 91177308-0d34-0410-b5e6-96231b3b80d8		2011-04-05 21:49:44 +00:00
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CodeGen	These tests no longer require linear scan because reserved register coalescing is now universal.	2011-04-05 21:40:41 +00:00
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MC	ARM disassembler was erroneously accepting an invalid LSL instruction.	2011-04-05 21:49:44 +00:00
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Transforms	InstCombine optimizes gep(bitcast(x)) even when the bitcasts casts away address	2011-04-05 14:29:52 +00:00
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