Johnny Chen c584e317e9 ARM disassembler was erroneously accepting an invalid LSL instruction. ... For register-controlled shifts, we should check that the encoding constraint Inst{7} = 0 and Inst{4} = 1 is satisfied. rdar://problem/9237693 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128941 91177308-0d34-0410-b5e6-96231b3b80d8		2011-04-05 21:49:44 +00:00
..
arm-tests.txt	The r128085 checkin modified the operand ordering for MRC/MRC2 instructions.	2011-04-05 20:32:23 +00:00
dg.exp
invalid-CPS2p-arm.txt
invalid-CPS3p-arm.txt
invalid-LDC-form-arm.txt	Add a test case for a malformed LDC/LDC2 instructions with PUDW = 0b0000, which	2011-03-31 20:54:30 +00:00
invalid-LDRrs-arm.txt	Fix single word and unsigned byte data transfer instruction encodings so that	2011-03-31 19:28:35 +00:00
invalid-LDRT-arm.txt	Fix a LDRT/LDRBT decoding bug where for Encoding A2, if Inst{4} != 0, we should reject the instruction	2011-04-01 20:21:38 +00:00
invalid-MOVr-arm.txt	Fixed MOVr for "should be" encoding bits for Inst{19-16} = 0b0000.	2011-04-01 23:30:25 +00:00
invalid-MOVs-arm.txt	MOVs should have Inst{19-16} as 0b0000, otherwise, the instruction is UNPREDICTABLE.	2011-04-01 23:15:50 +00:00
invalid-MOVs-LSL-arm.txt	ARM disassembler was erroneously accepting an invalid LSL instruction.	2011-04-05 21:49:44 +00:00
invalid-RFEorLDMIA-arm.txt	Fix SRS/SRSW encoding bits.	2011-04-05 00:16:18 +00:00
invalid-SRS-arm.txt	Fix SRS/SRSW encoding bits.	2011-04-05 00:16:18 +00:00
invalid-UMAAL-arm.txt	Check for invalid register encodings for UMAAL and friends where:	2011-04-05 17:43:10 +00:00
invalid-VLDMSDB_UPD-arm.txt
neon-tests.txt	Fix incorrect alignment for NEON VST2b32_UPD.	2011-04-04 20:35:31 +00:00
thumb-printf.txt	ARM disassembler should flag (rGPRRegClassID, r13|r15) as an error.	2011-04-05 19:42:11 +00:00
thumb-tests.txt	ARM disassembler should flag (rGPRRegClassID, r13|r15) as an error.	2011-04-05 19:42:11 +00:00