Richard Osborne c6ff29713d [XCore] The RRegs register class is a superset of GRRegs. ... At the time when the XCore backend was added there were some issues with with overlapping register classes but these all seem to be fixed now. Describing the register classes correctly allow us to get rid of a codegen only instruction (LDAWSP_lru6_RRegs) and it means we can disassemble ru6 instructions that use registers above r11. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178782 91177308-0d34-0410-b5e6-96231b3b80d8		2013-04-04 19:57:46 +00:00
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AArch64	AArch64: implement ETMv4 trace system registers.	2013-04-03 12:31:29 +00:00
ARM	Fix issue with disassembler decoding CBZ/CBNZ immediates as negatives when the upper bit is set.	2013-03-28 19:22:28 +00:00
MBlaze
Mips	This is a resubmittal. For some reason it broke the bots yesterday	2013-01-17 00:28:20 +00:00
X86	x86 -- disassemble the REP/REPNE prefix when needed	2013-03-25 18:59:38 +00:00
XCore	[XCore] The RRegs register class is a superset of GRRegs.	2013-04-04 19:57:46 +00:00