Evan Cheng c892aeb266 Optimize a couple of common patterns involving conditional moves where the false ... value is zero. Instead of a cmov + op, issue an conditional op instead. e.g. cmp r9, r4 mov r4, #0 moveq r4, #1 orr lr, lr, r4 should be: cmp r9, r4 orreq lr, lr, #1 That is, optimize (or x, (cmov 0, y, cond)) to (or.cond x, y). Similarly extend this to xor as well as (and x, (cmov -1, y, cond)) => (and.cond x, y). It's possible to extend this to ADD and SUB but I don't think they are common. rdar://8659097 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151224 91177308-0d34-0410-b5e6-96231b3b80d8		2012-02-23 01:19:06 +00:00
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Analysis	Remove extra semi-colons.	2012-02-22 17:25:00 +00:00
Archive
AsmParser
Bitcode
CodeGen	Handle regmasks in CriticalAntiDepBreaker.	2012-02-23 01:15:26 +00:00
DebugInfo
ExecutionEngine	Remove dead code. Improve llvm_unreachable text. Simplify some control flow.	2012-02-19 11:37:01 +00:00
Linker
MC	MC: Fix the MCNullStreamer which was broken in r147763.	2012-02-22 23:49:50 +00:00
Object	Remove static ctor.	2012-02-22 13:42:11 +00:00
Support	Remove extra semi-colons.	2012-02-22 17:25:00 +00:00
TableGen	Add Foreach Loop	2012-02-22 16:09:41 +00:00
Target	Optimize a couple of common patterns involving conditional moves where the false	2012-02-23 01:19:06 +00:00
Transforms	Use the target-aware constant folder on expressions to improve the chance	2012-02-21 22:08:06 +00:00
VMCore	Remove extra semi-colons.	2012-02-22 17:25:00 +00:00
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