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52d2b0ed00
before reglist were not properly handled with respect to IT Block. Fix that by creating a new method ARMBasicMCBuilder::DoPredicateOperands() used by those instructions for disassembly. Add a test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101974 91177308-0d34-0410-b5e6-96231b3b80d8
263 lines
8.9 KiB
C++
263 lines
8.9 KiB
C++
//===- ARMDisassemblerCore.h - ARM disassembler helpers ---------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file is part of the ARM Disassembler.
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//
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// The first part defines the enumeration type of ARM instruction format, which
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// specifies the encoding used by the instruction, as well as a helper function
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// to convert the enums to printable char strings.
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//
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// It also contains code to represent the concepts of Builder and DisassembleFP
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// to solve the problem of disassembling an ARM instr.
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//
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//===----------------------------------------------------------------------===//
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#ifndef ARMDISASSEMBLERCORE_H
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#define ARMDISASSEMBLERCORE_H
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#include "llvm/MC/MCInst.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "ARMInstrInfo.h"
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#include "ARMDisassembler.h"
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namespace llvm {
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class ARMUtils {
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public:
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static const char *OpcodeName(unsigned Opcode);
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};
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/////////////////////////////////////////////////////
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// //
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// Enums and Utilities for ARM Instruction Format //
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// //
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/////////////////////////////////////////////////////
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#define ARM_FORMATS \
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ENTRY(ARM_FORMAT_PSEUDO, 0) \
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ENTRY(ARM_FORMAT_MULFRM, 1) \
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ENTRY(ARM_FORMAT_BRFRM, 2) \
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ENTRY(ARM_FORMAT_BRMISCFRM, 3) \
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ENTRY(ARM_FORMAT_DPFRM, 4) \
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ENTRY(ARM_FORMAT_DPSOREGFRM, 5) \
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ENTRY(ARM_FORMAT_LDFRM, 6) \
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ENTRY(ARM_FORMAT_STFRM, 7) \
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ENTRY(ARM_FORMAT_LDMISCFRM, 8) \
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ENTRY(ARM_FORMAT_STMISCFRM, 9) \
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ENTRY(ARM_FORMAT_LDSTMULFRM, 10) \
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ENTRY(ARM_FORMAT_LDSTEXFRM, 11) \
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ENTRY(ARM_FORMAT_ARITHMISCFRM, 12) \
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ENTRY(ARM_FORMAT_EXTFRM, 13) \
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ENTRY(ARM_FORMAT_VFPUNARYFRM, 14) \
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ENTRY(ARM_FORMAT_VFPBINARYFRM, 15) \
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ENTRY(ARM_FORMAT_VFPCONV1FRM, 16) \
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ENTRY(ARM_FORMAT_VFPCONV2FRM, 17) \
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ENTRY(ARM_FORMAT_VFPCONV3FRM, 18) \
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ENTRY(ARM_FORMAT_VFPCONV4FRM, 19) \
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ENTRY(ARM_FORMAT_VFPCONV5FRM, 20) \
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ENTRY(ARM_FORMAT_VFPLDSTFRM, 21) \
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ENTRY(ARM_FORMAT_VFPLDSTMULFRM, 22) \
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ENTRY(ARM_FORMAT_VFPMISCFRM, 23) \
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ENTRY(ARM_FORMAT_THUMBFRM, 24) \
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ENTRY(ARM_FORMAT_NEONFRM, 25) \
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ENTRY(ARM_FORMAT_NEONGETLNFRM, 26) \
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ENTRY(ARM_FORMAT_NEONSETLNFRM, 27) \
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ENTRY(ARM_FORMAT_NEONDUPFRM, 28) \
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ENTRY(ARM_FORMAT_MISCFRM, 29) \
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ENTRY(ARM_FORMAT_THUMBMISCFRM, 30) \
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ENTRY(ARM_FORMAT_NLdSt, 31) \
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ENTRY(ARM_FORMAT_N1RegModImm, 32) \
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ENTRY(ARM_FORMAT_N2Reg, 33) \
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ENTRY(ARM_FORMAT_NVCVT, 34) \
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ENTRY(ARM_FORMAT_NVecDupLn, 35) \
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ENTRY(ARM_FORMAT_N2RegVecShL, 36) \
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ENTRY(ARM_FORMAT_N2RegVecShR, 37) \
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ENTRY(ARM_FORMAT_N3Reg, 38) \
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ENTRY(ARM_FORMAT_N3RegVecSh, 39) \
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ENTRY(ARM_FORMAT_NVecExtract, 40) \
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ENTRY(ARM_FORMAT_NVecMulScalar, 41) \
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ENTRY(ARM_FORMAT_NVTBL, 42)
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// ARM instruction format specifies the encoding used by the instruction.
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#define ENTRY(n, v) n = v,
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typedef enum {
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ARM_FORMATS
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ARM_FORMAT_NA
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} ARMFormat;
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#undef ENTRY
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// Converts enum to const char*.
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static const inline char *stringForARMFormat(ARMFormat form) {
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#define ENTRY(n, v) case n: return #n;
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switch(form) {
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ARM_FORMATS
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case ARM_FORMAT_NA:
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default:
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return "";
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}
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#undef ENTRY
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}
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/// Expands on the enum definitions from ARMBaseInstrInfo.h.
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/// They are being used by the disassembler implementation.
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namespace ARMII {
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enum {
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NEONRegMask = 15,
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GPRRegMask = 15,
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NEON_RegRdShift = 12,
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NEON_D_BitShift = 22,
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NEON_RegRnShift = 16,
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NEON_N_BitShift = 7,
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NEON_RegRmShift = 0,
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NEON_M_BitShift = 5
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};
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}
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/// Utility function for extracting [From, To] bits from a uint32_t.
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static inline unsigned slice(uint32_t Bits, unsigned From, unsigned To) {
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assert(From < 32 && To < 32 && From >= To);
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return (Bits >> To) & ((1 << (From - To + 1)) - 1);
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}
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/// Utility function for setting [From, To] bits to Val for a uint32_t.
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static inline void setSlice(uint32_t &Bits, unsigned From, unsigned To,
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uint32_t Val) {
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assert(From < 32 && To < 32 && From >= To);
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uint32_t Mask = ((1 << (From - To + 1)) - 1);
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Bits &= ~(Mask << To);
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Bits |= (Val & Mask) << To;
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}
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/// Various utilities for checking the target specific flags.
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/// A unary data processing instruction doesn't have an Rn operand.
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static inline bool isUnaryDP(unsigned TSFlags) {
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return (TSFlags & ARMII::UnaryDP);
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}
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/// This four-bit field describes the addressing mode used.
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/// See also ARMBaseInstrInfo.h.
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static inline unsigned getAddrMode(unsigned TSFlags) {
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return (TSFlags & ARMII::AddrModeMask);
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}
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/// {IndexModePre, IndexModePost}
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/// Only valid for load and store ops.
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/// See also ARMBaseInstrInfo.h.
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static inline unsigned getIndexMode(unsigned TSFlags) {
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return (TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift;
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}
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/// Pre-/post-indexed operations define an extra $base_wb in the OutOperandList.
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static inline bool isPrePostLdSt(unsigned TSFlags) {
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return (TSFlags & ARMII::IndexModeMask) != 0;
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}
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// Forward declaration.
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class ARMBasicMCBuilder;
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// Builder Object is mostly ignored except in some Thumb disassemble functions.
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typedef ARMBasicMCBuilder *BO;
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/// DisassembleFP - DisassembleFP points to a function that disassembles an insn
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/// and builds the MCOperand list upon disassembly. It returns false on failure
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/// or true on success. The number of operands added is updated upon success.
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typedef bool (*DisassembleFP)(MCInst &MI, unsigned Opcode, uint32_t insn,
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unsigned short NumOps, unsigned &NumOpsAdded, BO Builder);
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/// CreateMCBuilder - Return an ARMBasicMCBuilder that can build up the MC
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/// infrastructure of an MCInst given the Opcode and Format of the instr.
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/// Return NULL if it fails to create/return a proper builder. API clients
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/// are responsible for freeing up of the allocated memory. Cacheing can be
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/// performed by the API clients to improve performance.
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extern ARMBasicMCBuilder *CreateMCBuilder(unsigned Opcode, ARMFormat Format);
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/// ARMBasicMCBuilder - ARMBasicMCBuilder represents an ARM MCInst builder that
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/// knows how to build up the MCOperand list.
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class ARMBasicMCBuilder {
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friend ARMBasicMCBuilder *CreateMCBuilder(unsigned Opcode, ARMFormat Format);
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unsigned Opcode;
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ARMFormat Format;
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unsigned short NumOps;
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DisassembleFP Disasm;
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Session *SP;
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int Err; // !=0 if the builder encounters some error condition during build.
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private:
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/// Opcode, Format, and NumOperands make up an ARM Basic MCBuilder.
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ARMBasicMCBuilder(unsigned opc, ARMFormat format, unsigned short num);
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public:
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ARMBasicMCBuilder(ARMBasicMCBuilder &B)
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: Opcode(B.Opcode), Format(B.Format), NumOps(B.NumOps), Disasm(B.Disasm),
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SP(B.SP) {
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Err = 0;
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}
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virtual ~ARMBasicMCBuilder() {}
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void SetSession(Session *sp) {
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SP = sp;
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}
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void SetErr(int ErrCode) {
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Err = ErrCode;
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}
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/// DoPredicateOperands - DoPredicateOperands process the predicate operands
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/// of some Thumb instructions which come before the reglist operands. It
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/// returns true if the two predicate operands have been processed.
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bool DoPredicateOperands(MCInst& MI, unsigned Opcode,
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uint32_t insn, unsigned short NumOpsRemaning);
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/// TryPredicateAndSBitModifier - TryPredicateAndSBitModifier tries to process
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/// the possible Predicate and SBitModifier, to build the remaining MCOperand
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/// constituents.
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bool TryPredicateAndSBitModifier(MCInst& MI, unsigned Opcode,
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uint32_t insn, unsigned short NumOpsRemaning);
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/// InITBlock - InITBlock returns true if we are inside an IT block.
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bool InITBlock() {
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if (SP)
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return SP->ITCounter > 0;
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return false;
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}
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/// Build - Build delegates to BuildIt to perform the heavy liftling. After
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/// that, it invokes RunBuildAfterHook where some housekeepings can be done.
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virtual bool Build(MCInst &MI, uint32_t insn) {
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bool Status = BuildIt(MI, insn);
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return RunBuildAfterHook(Status, MI, insn);
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}
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/// BuildIt - BuildIt performs the build step for this ARM Basic MC Builder.
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/// The general idea is to set the Opcode for the MCInst, followed by adding
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/// the appropriate MCOperands to the MCInst. ARM Basic MC Builder delegates
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/// to the Format-specific disassemble function for disassembly, followed by
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/// TryPredicateAndSBitModifier() for PredicateOperand and OptionalDefOperand
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/// which follow the Dst/Src Operands.
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virtual bool BuildIt(MCInst &MI, uint32_t insn);
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/// RunBuildAfterHook - RunBuildAfterHook performs operations deemed necessary
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/// after BuildIt is finished.
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virtual bool RunBuildAfterHook(bool Status, MCInst &MI, uint32_t insn);
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private:
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/// Get condition of the current IT instruction.
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unsigned GetITCond() {
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assert(SP);
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return slice(SP->ITState, 7, 4);
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}
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};
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} // namespace llvm
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#endif
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