Jim Grosbach 80d01dd3d1 ARM assembly parsing of MRS instruction. ...

Teach the parser to recognize the APSR and SPSR system register names. Add
and update tests accordingly.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135527 91177308-0d34-0410-b5e6-96231b3b80d8

2011-07-19 21:59:29 +00:00

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Analysis

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Archive

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Assembler

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Bindings/Ocaml

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Bitcode

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BugPoint

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CodeGen

Use the correct opcodes: SLLV/SRLV or AND must be used instead of SLL/SRL or

2011-07-19 20:34:00 +00:00

DebugInfo

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ExecutionEngine

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Feature

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FrontendAda

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FrontendC

More minor adjustments.

2011-07-16 07:28:35 +00:00

FrontendC++

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FrontendFortran

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FrontendObjC

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FrontendObjC++

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Integer

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lib

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Linker

fix rdar://9776316 - type remapping needed for inline asm blobs,

2011-07-15 23:18:40 +00:00

LLVMC

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MC

ARM assembly parsing of MRS instruction.

2011-07-19 21:59:29 +00:00

Object

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Other

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Scripts

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TableGen

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Transforms

Remove bogus test: for all possible inputs of %X, the 'sub nsw' is guaranteed

2011-07-19 08:22:57 +00:00

Unit

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Verifier

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CMakeLists.txt

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lit.cfg

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lit.site.cfg.in

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Makefile

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Makefile.tests

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site.exp.in

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TestRunner.sh

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