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c92d72abd0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165565 91177308-0d34-0410-b5e6-96231b3b80d8
96 lines
3.5 KiB
C++
96 lines
3.5 KiB
C++
//===-- llvm/CodeGen/TargetSchedule.h - Sched Machine Model -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines a wrapper around MCSchedModel that allows the interface to
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// benefit from information currently only available in TargetInstrInfo.
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// Ideally, the scheduling interface would be fully defined in the MC layer.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_TARGETSCHEDMODEL_H
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#define LLVM_TARGET_TARGETSCHEDMODEL_H
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#include "llvm/MC/MCSchedule.h"
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#include "llvm/MC/MCInstrItineraries.h"
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namespace llvm {
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class TargetRegisterInfo;
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class TargetSubtargetInfo;
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class TargetInstrInfo;
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class MachineInstr;
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/// Provide an instruction scheduling machine model to CodeGen passes.
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class TargetSchedModel {
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// For efficiency, hold a copy of the statically defined MCSchedModel for this
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// processor.
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MCSchedModel SchedModel;
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InstrItineraryData InstrItins;
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const TargetSubtargetInfo *STI;
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const TargetInstrInfo *TII;
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public:
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TargetSchedModel(): STI(0), TII(0) {}
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/// \brief Initialize the machine model for instruction scheduling.
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///
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/// The machine model API keeps a copy of the top-level MCSchedModel table
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/// indices and may query TargetSubtargetInfo and TargetInstrInfo to resolve
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/// dynamic properties.
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void init(const MCSchedModel &sm, const TargetSubtargetInfo *sti,
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const TargetInstrInfo *tii);
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/// \brief TargetInstrInfo getter.
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const TargetInstrInfo *getInstrInfo() const { return TII; }
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/// \brief Return true if this machine model includes an instruction-level
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/// scheduling model.
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///
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/// This is more detailed than the course grain IssueWidth and default
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/// latency properties, but separate from the per-cycle itinerary data.
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bool hasInstrSchedModel() const;
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/// \brief Return true if this machine model includes cycle-to-cycle itinerary
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/// data.
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///
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/// This models scheduling at each stage in the processor pipeline.
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bool hasInstrItineraries() const;
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/// \brief Compute operand latency based on the available machine model.
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///
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/// Computes and return the latency of the given data dependent def and use
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/// when the operand indices are already known. UseMI may be NULL for an
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/// unknown user.
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///
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/// FindMin may be set to get the minimum vs. expected latency. Minimum
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/// latency is used for scheduling groups, while expected latency is for
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/// instruction cost and critical path.
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unsigned computeOperandLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
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const MachineInstr *UseMI, unsigned UseOperIdx,
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bool FindMin) const;
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/// \brief Identify the processor corresponding to the current subtarget.
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unsigned getProcessorID() const { return SchedModel.getProcessorID(); }
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/// \brief Maximum number of micro-ops that may be scheduled per cycle.
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unsigned getIssueWidth() const { return SchedModel.IssueWidth; }
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private:
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/// getDefLatency is a helper for computeOperandLatency. Return the
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/// instruction's latency if operand lookup is not required.
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/// Otherwise return -1.
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int getDefLatency(const MachineInstr *DefMI, bool FindMin) const;
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/// Return the MCSchedClassDesc for this instruction.
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const MCSchedClassDesc *resolveSchedClass(const MachineInstr *MI) const;
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};
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} // namespace llvm
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#endif
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