Vincent Lejeune 69239a98b6 R600: Fix LowerUDIVREM ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194153 91177308-0d34-0410-b5e6-96231b3b80d8		2013-11-06 17:36:04 +00:00
..
AArch64	Implement AArch64 Neon instruction set Perm.	2013-11-06 03:35:27 +00:00
ARM	Enable optimization of sin / cos pair into call to __sincos_stret for iOS7+.	2013-11-03 06:14:38 +00:00
CPP
Generic	Change objectsize intrinsic to accept different address spaces.	2013-10-07 18:06:48 +00:00
Hexagon
Inputs
Mips	Fix r194019 as requested by Eric Christopher.	2013-11-05 08:14:14 +00:00
MSP430	Make sure SP is always aligned on a 2 byte boundary	2013-10-24 09:32:31 +00:00
NVPTX	[NVPTX] Switch from StrongPHIElimination to PHIElimination in NVPTXTargetMachine, and add some missing optimization passes to addOptimizedRegAlloc	2013-10-11 12:39:39 +00:00
PowerPC	Convert another llc -filetype=obj test.	2013-10-28 22:17:19 +00:00
R600	R600: Fix LowerUDIVREM	2013-11-06 17:36:04 +00:00
SPARC	[SparcV9] Handle i64 <-> float conversions in sparcv9 mode.	2013-11-03 12:28:40 +00:00
SystemZ	[SystemZ] Automatically detect zEC12 and z196 hosts	2013-10-31 12:14:17 +00:00
Thumb	17309 ARM backend incorrectly lowers COPY_STRUCT_BYVAL_I32 for thumb1 targets	2013-10-17 19:52:05 +00:00
Thumb2	MachineSink: Fix and tweak critical-edge breaking heuristic.	2013-10-14 16:57:17 +00:00
X86	Slightly change the way stackmap and patchpoint intrinsics are lowered.	2013-11-05 22:44:04 +00:00
XCore	XCore target fix bug in emitArrayBound() causing segmentation fault	2013-10-11 10:27:13 +00:00