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https://github.com/c64scene-ar/llvm-6502.git
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58269b9732
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126108 91177308-0d34-0410-b5e6-96231b3b80d8
324 lines
8.9 KiB
C++
324 lines
8.9 KiB
C++
//===-- DelaySlotFiller.cpp - SPARC delay slot filler ---------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This is a simple local pass that attempts to fill delay slots with useful
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// instructions. If no instructions can be moved into the delay slot, then a
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// NOP is placed.
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "delay-slot-filler"
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#include "Sparc.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/Statistic.h"
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using namespace llvm;
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STATISTIC(FilledSlots, "Number of delay slots filled");
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static cl::opt<bool> DisableDelaySlotFiller(
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"disable-sparc-delay-filler",
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cl::init(false),
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cl::desc("Disable the Sparc delay slot filler."),
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cl::Hidden);
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namespace {
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struct Filler : public MachineFunctionPass {
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/// Target machine description which we query for reg. names, data
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/// layout, etc.
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///
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TargetMachine &TM;
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const TargetInstrInfo *TII;
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static char ID;
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Filler(TargetMachine &tm)
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: MachineFunctionPass(ID), TM(tm), TII(tm.getInstrInfo()) { }
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virtual const char *getPassName() const {
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return "SPARC Delay Slot Filler";
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}
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bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
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bool runOnMachineFunction(MachineFunction &F) {
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bool Changed = false;
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for (MachineFunction::iterator FI = F.begin(), FE = F.end();
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FI != FE; ++FI)
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Changed |= runOnMachineBasicBlock(*FI);
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return Changed;
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}
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bool isDelayFiller(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator candidate);
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void insertCallUses(MachineBasicBlock::iterator MI,
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SmallSet<unsigned, 32>& RegUses);
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void insertDefsUses(MachineBasicBlock::iterator MI,
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SmallSet<unsigned, 32>& RegDefs,
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SmallSet<unsigned, 32>& RegUses);
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bool IsRegInSet(SmallSet<unsigned, 32>& RegSet,
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unsigned Reg);
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bool delayHasHazard(MachineBasicBlock::iterator candidate,
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bool &sawLoad, bool &sawStore,
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SmallSet<unsigned, 32> &RegDefs,
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SmallSet<unsigned, 32> &RegUses);
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MachineBasicBlock::iterator
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findDelayInstr(MachineBasicBlock &MBB, MachineBasicBlock::iterator slot);
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bool needsUnimp(MachineBasicBlock::iterator I, unsigned &StructSize);
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};
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char Filler::ID = 0;
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} // end of anonymous namespace
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/// createSparcDelaySlotFillerPass - Returns a pass that fills in delay
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/// slots in Sparc MachineFunctions
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///
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FunctionPass *llvm::createSparcDelaySlotFillerPass(TargetMachine &tm) {
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return new Filler(tm);
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}
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/// runOnMachineBasicBlock - Fill in delay slots for the given basic block.
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/// We assume there is only one delay slot per delayed instruction.
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///
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bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
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bool Changed = false;
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for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I)
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if (I->getDesc().hasDelaySlot()) {
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MachineBasicBlock::iterator D = MBB.end();
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MachineBasicBlock::iterator J = I;
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if (!DisableDelaySlotFiller)
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D = findDelayInstr(MBB, I);
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++FilledSlots;
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Changed = true;
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if (D == MBB.end())
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BuildMI(MBB, ++J, I->getDebugLoc(), TII->get(SP::NOP));
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else
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MBB.splice(++J, &MBB, D);
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unsigned structSize = 0;
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if (needsUnimp(I, structSize)) {
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MachineBasicBlock::iterator J = I;
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++J; //skip the delay filler.
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BuildMI(MBB, ++J, I->getDebugLoc(),
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TII->get(SP::UNIMP)).addImm(structSize);
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}
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}
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return Changed;
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}
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MachineBasicBlock::iterator
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Filler::findDelayInstr(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator slot)
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{
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SmallSet<unsigned, 32> RegDefs;
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SmallSet<unsigned, 32> RegUses;
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bool sawLoad = false;
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bool sawStore = false;
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MachineBasicBlock::iterator I = slot;
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if (slot->getOpcode() == SP::RET)
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return MBB.end();
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if (slot->getOpcode() == SP::RETL) {
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--I;
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if (I->getOpcode() != SP::RESTORErr)
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return MBB.end();
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//change retl to ret
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slot->setDesc(TII->get(SP::RET));
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return I;
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}
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//Call's delay filler can def some of call's uses.
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if (slot->getDesc().isCall())
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insertCallUses(slot, RegUses);
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else
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insertDefsUses(slot, RegDefs, RegUses);
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bool done = false;
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while (!done) {
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done = (I == MBB.begin());
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if (!done)
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--I;
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// skip debug value
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if (I->isDebugValue())
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continue;
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if (I->hasUnmodeledSideEffects()
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|| I->isInlineAsm()
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|| I->isLabel()
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|| I->getDesc().hasDelaySlot()
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|| isDelayFiller(MBB, I))
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break;
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if (delayHasHazard(I, sawLoad, sawStore, RegDefs, RegUses)) {
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insertDefsUses(I, RegDefs, RegUses);
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continue;
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}
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return I;
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}
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return MBB.end();
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}
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bool Filler::delayHasHazard(MachineBasicBlock::iterator candidate,
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bool &sawLoad,
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bool &sawStore,
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SmallSet<unsigned, 32> &RegDefs,
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SmallSet<unsigned, 32> &RegUses)
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{
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if (candidate->isImplicitDef() || candidate->isKill())
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return true;
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if (candidate->getDesc().mayLoad()) {
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sawLoad = true;
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if (sawStore)
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return true;
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}
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if (candidate->getDesc().mayStore()) {
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if (sawStore)
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return true;
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sawStore = true;
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if (sawLoad)
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return true;
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}
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for (unsigned i = 0, e = candidate->getNumOperands(); i!= e; ++i) {
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const MachineOperand &MO = candidate->getOperand(i);
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if (!MO.isReg())
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continue; // skip
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unsigned Reg = MO.getReg();
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if (MO.isDef()) {
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//check whether Reg is defined or used before delay slot.
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if (IsRegInSet(RegDefs, Reg) || IsRegInSet(RegUses, Reg))
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return true;
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}
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if (MO.isUse()) {
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//check whether Reg is defined before delay slot.
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if (IsRegInSet(RegDefs, Reg))
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return true;
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}
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}
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return false;
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}
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void Filler::insertCallUses(MachineBasicBlock::iterator MI,
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SmallSet<unsigned, 32>& RegUses)
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{
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switch(MI->getOpcode()) {
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default: llvm_unreachable("Unknown opcode.");
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case SP::CALL: break;
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case SP::JMPLrr:
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case SP::JMPLri:
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assert(MI->getNumOperands() >= 2);
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const MachineOperand &Reg = MI->getOperand(0);
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assert(Reg.isReg() && "JMPL first operand is not a register.");
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assert(Reg.isUse() && "JMPL first operand is not a use.");
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RegUses.insert(Reg.getReg());
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const MachineOperand &RegOrImm = MI->getOperand(1);
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if (RegOrImm.isImm())
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break;
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assert(RegOrImm.isReg() && "JMPLrr second operand is not a register.");
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assert(RegOrImm.isUse() && "JMPLrr second operand is not a use.");
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RegUses.insert(RegOrImm.getReg());
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break;
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}
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}
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//Insert Defs and Uses of MI into the sets RegDefs and RegUses.
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void Filler::insertDefsUses(MachineBasicBlock::iterator MI,
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SmallSet<unsigned, 32>& RegDefs,
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SmallSet<unsigned, 32>& RegUses)
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{
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg())
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continue;
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unsigned Reg = MO.getReg();
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if (Reg == 0)
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continue;
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if (MO.isDef())
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RegDefs.insert(Reg);
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if (MO.isUse())
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RegUses.insert(Reg);
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}
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}
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//returns true if the Reg or its alias is in the RegSet.
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bool Filler::IsRegInSet(SmallSet<unsigned, 32>& RegSet, unsigned Reg)
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{
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if (RegSet.count(Reg))
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return true;
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// check Aliased Registers
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for (const unsigned *Alias = TM.getRegisterInfo()->getAliasSet(Reg);
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*Alias; ++ Alias)
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if (RegSet.count(*Alias))
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return true;
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return false;
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}
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// return true if the candidate is a delay filler.
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bool Filler::isDelayFiller(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator candidate)
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{
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if (candidate == MBB.begin())
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return false;
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if (candidate->getOpcode() == SP::UNIMP)
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return true;
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const TargetInstrDesc &prevdesc = (--candidate)->getDesc();
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return prevdesc.hasDelaySlot();
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}
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bool Filler::needsUnimp(MachineBasicBlock::iterator I, unsigned &StructSize)
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{
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if (!I->getDesc().isCall())
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return false;
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unsigned structSizeOpNum = 0;
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switch (I->getOpcode()) {
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default: llvm_unreachable("Unknown call opcode.");
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case SP::CALL: structSizeOpNum = 1; break;
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case SP::JMPLrr:
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case SP::JMPLri: structSizeOpNum = 2; break;
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}
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const MachineOperand &MO = I->getOperand(structSizeOpNum);
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if (!MO.isImm())
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return false;
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StructSize = MO.getImm();
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return true;
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}
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