Quentin Colombet 2b7cdf09a1 ARM: Remove a (false) dependency on the memoryoperand's value as we do not use ...

it at the moment.
This allows to form more paired loads even when stack coloring pass destroys the
memoryoperand's value.

<rdar://problem/13978317>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184492 91177308-0d34-0410-b5e6-96231b3b80d8

2013-06-20 22:51:44 +00:00

..

AArch64

AArch64: remove accidental test output file.

2013-06-18 21:16:53 +00:00

ARM

ARM: Remove a (false) dependency on the memoryoperand's value as we do not use

2013-06-20 22:51:44 +00:00

CPP

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Generic

Drop @llvm.annotation and @llvm.ptr.annotation intrinsics during codegen.

2013-05-21 14:37:16 +00:00

Hexagon

Hexagon: Pass to replace tranfer/copy instructions into combine instruction

2013-05-14 18:54:06 +00:00

Inputs

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MBlaze

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Mips

[mips] Add an IR transformation pass that optimizes calls to sqrt.

2013-06-11 22:21:44 +00:00

MSP430

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NVPTX

[NVPTX] Remove old CONST_NOT_GEN address space that is not being used anymore and causes constants to be emitted in the global address space

2013-06-10 13:29:47 +00:00

PowerPC

[PowerPC] Disable fast-isel for existing -O0 tests for PowerPC.

2013-06-13 20:23:34 +00:00

R600

R600/SI: Expand sub for v2i32 and v4i32 for SI

2013-06-20 21:55:37 +00:00

SI

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SPARC

Switch spill weights from a basic loop depth estimation to BlockFrequencyInfo.

2013-06-17 19:00:36 +00:00

SystemZ

[SystemZ] Don't use LOAD and STORE REVERSED for volatile accesses

2013-05-31 13:25:22 +00:00

Thumb

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Thumb2

Cortex-R5 can issue Thumb2 integer division instructions.

2013-06-04 22:52:09 +00:00

X86

DebugInfo: don't use location lists when the location covers the whole function anyway

2013-06-20 00:25:24 +00:00

XCore

[XCore] Fix handling of functions where only the LR is spilled.

2013-05-09 16:43:42 +00:00