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https://github.com/c64scene-ar/llvm-6502.git
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e7d6df7353
consecutive addresses togther. This makes it easier for the post-allocation pass to form ldm / stm. This is step 1. We are still missing a lot of ldm / stm opportunities because of register allocation are not done in the desired order. More enhancements coming. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73291 91177308-0d34-0410-b5e6-96231b3b80d8
256 lines
8.7 KiB
C++
256 lines
8.7 KiB
C++
//===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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#include "ARMTargetMachine.h"
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#include "ARMTargetAsmInfo.h"
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#include "ARMFrameInfo.h"
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#include "ARM.h"
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#include "llvm/Module.h"
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#include "llvm/PassManager.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetMachineRegistry.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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static cl::opt<bool>
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EnablePreLdStOpti("arm-pre-alloc-loadstore-opti", cl::Hidden,
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cl::desc("Enable pre-regalloc load store optimization pass"));
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static cl::opt<bool> DisableLdStOpti("disable-arm-loadstore-opti", cl::Hidden,
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cl::desc("Disable load store optimization pass"));
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static cl::opt<bool> DisableIfConversion("disable-arm-if-conversion",cl::Hidden,
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cl::desc("Disable if-conversion pass"));
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/// ARMTargetMachineModule - Note that this is used on hosts that cannot link
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/// in a library unless there are references into the library. In particular,
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/// it seems that it is not possible to get things to work on Win32 without
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/// this. Though it is unused, do not remove it.
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extern "C" int ARMTargetMachineModule;
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int ARMTargetMachineModule = 0;
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// Register the target.
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static RegisterTarget<ARMTargetMachine> X("arm", "ARM");
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static RegisterTarget<ThumbTargetMachine> Y("thumb", "Thumb");
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// No assembler printer by default
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ARMTargetMachine::AsmPrinterCtorFn ARMTargetMachine::AsmPrinterCtor = 0;
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/// ThumbTargetMachine - Create an Thumb architecture model.
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///
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unsigned ThumbTargetMachine::getJITMatchQuality() {
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#if defined(__thumb__)
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return 10;
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#endif
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return 0;
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}
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unsigned ThumbTargetMachine::getModuleMatchQuality(const Module &M) {
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std::string TT = M.getTargetTriple();
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// Match thumb-foo-bar, as well as things like thumbv5blah-*
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if (TT.size() >= 6 &&
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(TT.substr(0, 6) == "thumb-" || TT.substr(0, 6) == "thumbv"))
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return 20;
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// If the target triple is something non-thumb, we don't match.
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if (!TT.empty()) return 0;
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if (M.getEndianness() == Module::LittleEndian &&
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M.getPointerSize() == Module::Pointer32)
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return 10; // Weak match
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else if (M.getEndianness() != Module::AnyEndianness ||
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M.getPointerSize() != Module::AnyPointerSize)
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return 0; // Match for some other target
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return getJITMatchQuality()/2;
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}
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ThumbTargetMachine::ThumbTargetMachine(const Module &M, const std::string &FS)
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: ARMTargetMachine(M, FS, true) {
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}
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/// TargetMachine ctor - Create an ARM architecture model.
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///
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ARMTargetMachine::ARMTargetMachine(const Module &M, const std::string &FS,
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bool isThumb)
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: Subtarget(M, FS, isThumb),
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DataLayout(Subtarget.isAPCS_ABI() ?
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// APCS ABI
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(isThumb ?
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std::string("e-p:32:32-f64:32:32-i64:32:32-"
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"i16:16:32-i8:8:32-i1:8:32-a:0:32") :
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std::string("e-p:32:32-f64:32:32-i64:32:32")) :
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// AAPCS ABI
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(isThumb ?
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std::string("e-p:32:32-f64:64:64-i64:64:64-"
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"i16:16:32-i8:8:32-i1:8:32-a:0:32") :
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std::string("e-p:32:32-f64:64:64-i64:64:64"))),
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InstrInfo(Subtarget),
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FrameInfo(Subtarget),
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JITInfo(),
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TLInfo(*this) {
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DefRelocModel = getRelocationModel();
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}
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unsigned ARMTargetMachine::getJITMatchQuality() {
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#if defined(__arm__)
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return 10;
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#endif
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return 0;
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}
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unsigned ARMTargetMachine::getModuleMatchQuality(const Module &M) {
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std::string TT = M.getTargetTriple();
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// Match arm-foo-bar, as well as things like armv5blah-*
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if (TT.size() >= 4 &&
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(TT.substr(0, 4) == "arm-" || TT.substr(0, 4) == "armv"))
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return 20;
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// If the target triple is something non-arm, we don't match.
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if (!TT.empty()) return 0;
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if (M.getEndianness() == Module::LittleEndian &&
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M.getPointerSize() == Module::Pointer32)
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return 10; // Weak match
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else if (M.getEndianness() != Module::AnyEndianness ||
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M.getPointerSize() != Module::AnyPointerSize)
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return 0; // Match for some other target
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return getJITMatchQuality()/2;
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}
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const TargetAsmInfo *ARMTargetMachine::createTargetAsmInfo() const {
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switch (Subtarget.TargetType) {
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case ARMSubtarget::isDarwin:
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return new ARMDarwinTargetAsmInfo(*this);
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case ARMSubtarget::isELF:
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return new ARMELFTargetAsmInfo(*this);
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default:
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return new ARMGenericTargetAsmInfo(*this);
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}
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}
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// Pass Pipeline Configuration
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bool ARMTargetMachine::addInstSelector(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel) {
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PM.add(createARMISelDag(*this));
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return false;
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}
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bool ARMTargetMachine::addPreRegAlloc(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel) {
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if (!EnablePreLdStOpti)
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return false;
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// FIXME: temporarily disabling load / store optimization pass for Thumb mode.
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if (OptLevel != CodeGenOpt::None && !DisableLdStOpti && !Subtarget.isThumb())
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PM.add(createARMLoadStoreOptimizationPass(true));
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return true;
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}
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bool ARMTargetMachine::addPreEmitPass(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel) {
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// FIXME: temporarily disabling load / store optimization pass for Thumb mode.
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if (OptLevel != CodeGenOpt::None && !DisableLdStOpti && !Subtarget.isThumb())
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PM.add(createARMLoadStoreOptimizationPass());
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if (OptLevel != CodeGenOpt::None &&
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!DisableIfConversion && !Subtarget.isThumb())
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PM.add(createIfConverterPass());
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PM.add(createARMConstantIslandPass());
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return true;
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}
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bool ARMTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel,
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bool Verbose,
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raw_ostream &Out) {
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// Output assembly language.
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assert(AsmPrinterCtor && "AsmPrinter was not linked in");
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if (AsmPrinterCtor)
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PM.add(AsmPrinterCtor(Out, *this, OptLevel, Verbose));
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return false;
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}
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bool ARMTargetMachine::addCodeEmitter(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel,
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bool DumpAsm,
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MachineCodeEmitter &MCE) {
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// FIXME: Move this to TargetJITInfo!
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if (DefRelocModel == Reloc::Default)
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setRelocationModel(Reloc::Static);
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// Machine code emitter pass for ARM.
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PM.add(createARMCodeEmitterPass(*this, MCE));
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if (DumpAsm) {
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assert(AsmPrinterCtor && "AsmPrinter was not linked in");
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if (AsmPrinterCtor)
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PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
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}
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return false;
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}
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bool ARMTargetMachine::addCodeEmitter(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel,
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bool DumpAsm,
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JITCodeEmitter &JCE) {
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// FIXME: Move this to TargetJITInfo!
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if (DefRelocModel == Reloc::Default)
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setRelocationModel(Reloc::Static);
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// Machine code emitter pass for ARM.
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PM.add(createARMJITCodeEmitterPass(*this, JCE));
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if (DumpAsm) {
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assert(AsmPrinterCtor && "AsmPrinter was not linked in");
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if (AsmPrinterCtor)
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PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
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}
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return false;
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}
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bool ARMTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel,
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bool DumpAsm,
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MachineCodeEmitter &MCE) {
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// Machine code emitter pass for ARM.
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PM.add(createARMCodeEmitterPass(*this, MCE));
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if (DumpAsm) {
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assert(AsmPrinterCtor && "AsmPrinter was not linked in");
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if (AsmPrinterCtor)
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PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
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}
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return false;
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}
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bool ARMTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel,
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bool DumpAsm,
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JITCodeEmitter &JCE) {
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// Machine code emitter pass for ARM.
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PM.add(createARMJITCodeEmitterPass(*this, JCE));
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if (DumpAsm) {
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assert(AsmPrinterCtor && "AsmPrinter was not linked in");
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if (AsmPrinterCtor)
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PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
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}
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return false;
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}
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